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KSZ8895MLU integrated 5-port 10/100 managed switch rev.1.1 micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com october 2011 m9999-100311-1.1 general description the KSZ8895MLU is a highly-integrated layer 2- managed 5-port switch with an optimized design and plentiful features, qualified to meet aec-q100 standard for automotive applications. it is designed for cost- sensitive 10/100mbps 5-port switch systems with on-chip termination, lowest power co nsumption and internal core power controller. these featur es will save more system cost. it has 1.4gbps high-performance memory bandwidth, shared memory based switch fabric with full non-blocking configuration. it al so provides an extensive feature set such as power management, programmble rate limit and priority ratio, tag/port-based vlan, packets filtering, quality of se rvice (qos) four-queues prioritization, management interface, and mib counters. port 5 is a mac 5 mii interface with phy mode. the sw5-mii interface can be connected to a processor with a mac mii interface. the KSZ8895MLU consists of 10/100 phys with patented and enhanced mixed-signal technology, media access control (mac) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. the KSZ8895MLU contains five macs and four intergrated phys. all phys support 10/100base-t/tx. all registers of macs and phys units can be managed by the spi interface or the smi interface. miim registers of the phys can be accessed through the mdc/mdio interface. eeprom can set all control registers for the unmanaged mode. datasheets and support documentation can be found on feature set such as power management, programmble rate limit and priority ratio, tag/port-based vlan, packets filtering, quality of se rvice (qos) four-queues prioritization, management interface, and mib counters. port 5 is a mac 5 mii interface with phy mode. the sw5-mii interface can be connected to a processor with a mac mii interface. the KSZ8895MLU provides multiple cpu control/data interfaces to effectively address both current and emerging fast ethernet applications. micrel?s web site at: www.micrel.com . functional diagram
micrel, inc. KSZ8895MLU october 2011 2 m9999-100311-1.1 features advanced switch features ? ieee 802.1q vlan support for up to 128 vlan groups (full-range 4096 of vlan ids). ? static mac table supports up to 32 entries. ? vlan id tag/untag options, per port basis. ? ieee 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress). ? programmable rate limiting at the ingress and egress on a per port basis. ? jitter-free per packet based rate-limiting support. ? broadcast storm protection with percentage control (global and per port basis). ? ieee 802.1d rapid spanning tree protocol rstp support. ? tail tag mode (1byte added before fcs) support at port 5 to inform the processor which ingress port receives the packet. ? 1.4gbps high-performance memory bandwidth and shared memory-based switch fabric with fully non- blocking configuration. ? mii with mac 5 on port 5, sw5-mii for mac 5 mii interface. ? enable/disable option for huge frame size up to 2000 bytes per frame. ? igmp v1/v2 snooping (ipv4) support for multicast packet filtering. ? ipv4/ipv6 qos support. ? support unknown unicast/multicast address and unknown vid packet filtering. ? self-address filtering. comprehensive configuration register access ? serial management interface (mdc/mdio) to all phys registers and smi interface (mdc/mdio) to all registers. ? high-speed spi (up to 25mhz) and i 2 c master interface to all internal registers. ? i/0 pins strapping and eeprom to program selective registers in unmanaged switch mode. ? control registers configurable on the fly (port-priority, 802.1p/d/q, an?). qos/cos packet prioritization support ? per port, 802.1p and diffserv-based. ? 1/2/4-queue qos prioritization selection. ? programmable weighted fair queuing for ratio control. ? re-mapping of 802.1p priority field per port basis. integrated 5-port 10/100 ethernet switch ? new generation switch with five macs and five phys fully compliant with ieee 802.3u standard. ? non-blocking switch fabric assures fast packet delivery by utilizing a 1k mac address lookup table and a store- and-forward architecture. ? on-chip 64kbyte memory for frame buffering (not shared with 1k unicast address table). ? full duplex ieee 802.3x flow control (pause) with force mode option. ? half-duplex back pre ssure flow control. ? hp auto mdi/mdi-x and ieee auto crossover support. ? port 5 mac5 sw5-mii interface supports phy mode and mac mode. ? 7-wire serial network interface (sni) support for legacy mac. ? per port led indicators for link, activity, and 10/100 speed. ? register port status support fo r link, activity, full/half duplex and 10/100 speed. ? on-chip terminations and internal biasing technology for cost down and lowest power consumption. switch monitoring features ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or mii. ? mib counters for fully-complia nt statistics gathering 34 mib counters per port. ? loop-back support for mac, phy, and remote diagnostic of failure. ? interrupt for the link change on any ports. low power dissipation ? full-chip hardware power-down. ? full-chip software power-down/per port software power down. ? energy-detect mode support < 100mw full-chip power consumption when all ports have no activity. ? very-low, full-chip power consumption (<0.5w), without extra power consumption on transformers. ? dynamic clock-tree shutdown feature. ? voltages: single 3.3v supply with 3.3v vddio and internal 1.2v ldo controller enabled or external 1.2v ldo solution: ? analog vddat 3.3v only ? vddio support 3.3v, 2.5v and 1.8v ? low 1.2v core power ? 0.13um cmos technology. ? industrial temperature range: ?40 o c to +85 o c. ? available in 128-pin lqfp, lead-free package. applications ? in-vehicle diagnostics (obd) ? high speed software download ? gateway switch ? head unit ? rear seat entertainment
micrel, inc. KSZ8895MLU october 2011 3 m9999-100311-1.1 ordering information part number temperature range package lead finish/grade KSZ8895MLU (automotive grade) ? 40 ? c to +85 ? c 128-pin lqfp pb-free/automotive revision history revision date summary of changes 1.0 03/16/11 initial 1.1 09/27/11 update some descriptions, updates for descripti ons of smi mode and igmp mode, update register default values, pins type and some parameters.
micrel, inc. KSZ8895MLU october 2011 4 m9999-100311-1.1 contents pin confi guration .............................................................................................................. .................................................... 8 pin descr iption ................................................................................................................ ...................................................... 9 pin for strap- in op tions....................................................................................................... ............................................... 15 introduc tion ................................................................................................................... ...................................................... 18 physical layer transceiver..................................................................................................... ........................................... 18 100base-tx tr ansmit ............................................................................................................ ......................................... 18 10base-t tr ansmit .............................................................................................................. ............................................ 19 10base-t re ceive ............................................................................................................... ............................................ 19 mdi/mdi-x auto crossover ....................................................................................................... ....................................... 19 auto-negot iation ............................................................................................................... ................................................ 21 on-chip terminat ion resistors .................................................................................................. ...................................... 22 internal 1.2v ldo cont roller ................................................................................................... ......................................... 22 power management ............................................................................................................... ............................................. 23 normal oper ation mode .......................................................................................................... ......................................... 23 energy dete ct mode ............................................................................................................. ............................................ 23 soft power-do wn mode........................................................................................................... ......................................... 24 power-savin g mode .............................................................................................................. ........................................... 24 port-based powe r-down mode ..................................................................................................... ................................... 24 switch core.................................................................................................................... ................................................... 24 address look-up ................................................................................................................ .............................................. 24 learning ....................................................................................................................... ..................................................... 24 migration ...................................................................................................................... ..................................................... 24 aging.......................................................................................................................... ....................................................... 24 forwarding ..................................................................................................................... ................................................... 25 switching engine ............................................................................................................... ............................................... 25 media access controll er (mac) o peration ........................................................................................ .............................. 25 mii interface operation ........................................................................................................ ............................................. 28 port 5 mac 5 sw5- mii interface ................................................................................................. ..................................... 28 sni interface operation ........................................................................................................ ............................................ 29 advanced func tionality......................................................................................................... ............................................. 31 qos priority support ........................................................................................................... .............................................. 31 port-based priority............................................................................................................ ................................................ 31 802.1p-based priority .......................................................................................................... ............................................. 31 spanning tree support.......................................................................................................... ........................................... 32 rapid spanning tr ee support .................................................................................................... ...................................... 33 tail taggi ng m ode .............................................................................................................. .............................................. 33
micrel, inc. KSZ8895MLU october 2011 5 m9999-100311-1.1 igmp support ................................................................................................................... ................................................ 34 port mirror ing support ......................................................................................................... ............................................. 35 vlan support ................................................................................................................... ................................................ 35 rate limiti ng support .......................................................................................................... ............................................. 36 ingress rate limit ............................................................................................................. ................................................ 36 egress rate limit.............................................................................................................. ................................................ 36 transmit queue ra tio programming ............................................................................................... ................................. 37 filtering for self-address, unknown unicast/multicast address an d unknown vid packet/ip multicast ........................ 37 configuration interf ace ........................................................................................................ ............................................. 37 register de scription ........................................................................................................... ................................................ 43 global regi sters............................................................................................................... ................................................... 45 port regi sters................................................................................................................. ..................................................... 55 advanced contro l registers..................................................................................................... ......................................... 65 data rate selecti on table in 100bt ............................................................................................. ..................................... 82 data rate selecti on table in 10bt .............................................................................................. ...................................... 82 static mac a ddress ta ble ....................................................................................................... .......................................... 84 vlan table ..................................................................................................................... ..................................................... 86 dynamic mac ad dress table ...................................................................................................... ...................................... 89 management information base (mib) counters..................................................................................... .......................... 91 miim regi sters ................................................................................................................. .................................................... 95 absolute maximum ratings (1) ............................................................................................................................... ............. 99 operating ratings (2) ............................................................................................................................... ............................. 99 electrical characteristics (4, 5) ............................................................................................................................... ............... 99 timing di agrams ................................................................................................................ ............................................... 101 eeprom timing.................................................................................................................. ........................................... 101 sni timing ..................................................................................................................... ................................................. 102 mii timing ..................................................................................................................... .................................................. 103 spi timing ..................................................................................................................... ................................................. 104 auto-negotiati on timi ng ........................................................................................................ ......................................... 106 reset timing................................................................................................................... ................................................ 107 reset circui t diagram.......................................................................................................... ........................................... 108 isolation transfor mer selection ................................................................................................ ...................................... 109 reference crysta l selection.................................................................................................... ......................................... 109 package info rmation............................................................................................................ ............................................. 110
micrel, inc. KSZ8895MLU october 2011 6 m9999-100311-1.1 list of figures figure 1. typical st raight cable connection ................................................................................. .................................... 20 figure 2. typical cr ossover cable connection ................................................................................ ................................. 20 figure 3. au to-negotiation .................................................................................................. ............................................... 22 figure 4. destination addres s look-up flow chart (stage 1).................................................................. ......................... 26 figure 5. destination addres s resolution flow chart (stage 2) ............................................................... ........................ 27 figure 6. 802.1p pr iority fiel d format ...................................................................................... ......................................... 31 figure 7. tail tag frame format ............................................................................................. .......................................... 33 figure 8. KSZ8895MLU eeprom configuration timing di agram.................................................................... ................ 37 figure 9. spi write data cycle .............................................................................................. ............................................ 39 figure 10. spi r ead data cycle ................................................................................................ .......................................... 39 figure 11. spi multiple write ................................................................................................. .............................................. 40 figure 12. spi multiple read .................................................................................................. ............................................. 40 figure 13. eeprom interface i nput receive timi ng diagram...................................................................... .................... 101 figure 14. eeprom interface outp ut transmit ti ming diagram.................................................................... .................. 101 figure 15. sni input timing ................................................................................................... ............................................ 102 figure 16. sni output timing .................................................................................................. .......................................... 102 figure 19. mac mode mii timing ? data received from mii ............................................................................................ 103 figure 20. mac mode m ii timing parameters ..................................................................................... ............................. 103 figure 21. spi input timing ................................................................................................... ............................................ 104 figure 22. spi output timing.................................................................................................. ........................................... 105 figure 23. auto-n egotiation timing ............................................................................................ ....................................... 106 figure 24. re set timing....................................................................................................... .............................................. 107 figure 25. recommen ded reset circuit.......................................................................................... .................................. 108 figure 26. recommended circuit for interfacing with cpu/fpga reset............................................................ .............. 108
micrel, inc. KSZ8895MLU october 2011 7 m9999-100311-1.1 list of tables table 1. mdi/mdi -x pin defi nitions .......................................................................................... ......................................... 19 table 2. internal function block status ..................................................................................... ........................................ 23 table 3. switch ma c 5 mii/turbo mii signals ................................................................................. .................................. 29 table 4. sni si gnals ........................................................................................................ .................................................. 30 table 5. tail tag rules ..................................................................................................... ................................................. 34 table 6. fid+da lo ok-up in the vlan mode .................................................................................... ............................... 35 table 7. fid+sa look -up in the vlan mode .................................................................................... ............................... 36 table 8. spi connections .................................................................................................... .............................................. 38 table 9. mii management interface fr ame fo rmat .............................................................................. ............................. 41 table 10. serial management interface (smi) frame fo rmat ...................................................................... ....................... 41 table 11. format of static mac table for r ead (32 en tries) .................................................................... .......................... 84 table 12. format of static ma c table for writes (32 entries) .................................................................. .......................... 85 table 13. format of static vlan table (suppor t max 4096 vlan id entries and 128 active vlans).............................. 86 table 14. vlan id and indirect registers ...................................................................................... ..................................... 88 table 15. format of dynamic mac address tabl e (1k entries) .................................................................... ..................... 89 table 16. port 1 mib counte r indirect memo ry offsets .......................................................................... ............................. 91 table 17. format of ?p er port? mi b counter .................................................................................... .................................... 92 table 18. all port dropp ed packet mib counters................................................................................ ................................ 92 table 19. format of all dropped packet mib counters........................................................................... ............................ 93 table 20. eeprom timing parameters ............................................................................................ ................................ 101 table 21. sni ti ming parameters............................................................................................... ....................................... 102 table 22. mac mode timing para meters.......................................................................................... ................................ 103 table 23. spi input timing pa rameters......................................................................................... .................................... 104 table 24. spi output timing pa rameters ........................................................................................ .................................. 105 table 24. auto-negotiati on timing pa rameters.................................................................................. ............................... 106 table 25. reset timing parameters ............................................................................................. ..................................... 107 table 26. qualifi ed magnetic vendors.......................................................................................... ..................................... 109 table 27. qualifi ed magnetic vendors.......................................................................................... ..................................... 109 table 28. typical referenc e crystal characteristics ........................................................................... .............................. 109
micrel, inc. KSZ8895MLU october 2011 8 m9999-100311-1.1 pin configuration 128-pin lqfp
micrel, inc. KSZ8895MLU october 2011 9 m9999-100311-1.1 pin description pin number pin name type (1) port pin function (2) 1 mdi-xdis ipd 1 ? 5 disable auto mdi/mdi-x. pd (default) = normal operation. pu = disable auto mdi/mdi-x on all ports. 2 gnda gnd analog ground. 3 vddar p 1.2v analog v dd . 4 rxp1 i 1 physical receive signal + (differential). 5 rxm1 i 1 physical receive signal ? (differential). 6 gnda gnd analog ground. 7 txp1 o 1 physical transmit signal + (differential). 8 txm1 o 1 physical transmit signal ? (differential). 9 vddat p 3.3v analog v dd . 10 rxp2 i 2 physical receive signal + (differential). 11 rxm2 i 2 physical receive signal ? (differential). 12 gnda gnd analog ground. 13 txp2 o 2 physical transmit signal + (differential). 14 txm2 o 2 physical transmit signal ? (differential). 15 vddar p 1.2v analog v dd . 16 gnda gnd analog ground. 17 iset set physical transmit output current. pull-down with a 12.4k ? 1% resistor. 18 vddat p 3.3v analog v dd . 19 rxp3 i 3 physical receive signal + (differential). 20 rxm3 i 3 physical receive signal - (differential). 21 gnda gnd analog ground. 22 txp3 o 3 physical transmit signal + (differential). 23 txm3 o 3 physical transmit signal ? (differential). 24 vddat p 3.3v analog v dd . 25 rxp4 i 4 physical receive signal + (differential). notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up dur ing reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down. otri = output tristated.
micrel, inc. KSZ8895MLU october 2011 10 m9999-100311-1.1 pin description (continued) pin number pin name type (1) port pin function (2) 26 rxm4 i 4 physical receive signal - (differential). 27 gnda gnd analog ground. 28 txp4 o 4 physical transmit signal + (differential). 29 txm4 o 4 physical transmit signal ? (differential). 30 gnda gnd analog ground. 31 vddar p 1.2v analog v dd . 32 rxp5 i 5 reserved for mlu. no connect. 33 rxm5 i 5 reserved for mlu. no connect. 34 gnda gnd analog ground. 35 txp5 o 5 reserved for mlu. no connect. 36 txm5 o 5 reserved for mlu. no connect. 37 vddat p 3.3v analog v dd . 38 nc nc no connect. 39 nc nc no connect. 40 nc nc no connect. 41 nc nc no connect. 42 nc nc no connect. 43 nc nc no connect. 44 nc nc no connect. 45 nc nc no connect. 46 nc nc no connect. 47 pwrdn_n ipu full-chip power down. active low. 48 intr_n opu interrupt. this pin is op en-drain output pin. 49 gndd gnd digital ground. 50 vddc p 1.2v digital core v dd . 51 pmtxen ipd 5 reserved for mlu. no connect. 52 pmtxd3 ipd 5 reserved for mlu. no connect. 53 pmtxd2 ipd 5 reserved for mlu. no connect. 54 pmtxd1 ipd 5 reserved for mlu. no connect. 55 pmtxd0 ipd 5 reserved for mlu. no connect. 56 pmtxer ipd 5 reserved for mlu. no connect. 57 pmtxc i/o 5 reserved for mlu. no connect. 58 gndd gnd digital ground. 59 vddio p 3.3v, 2.5v or 1.8v digital v dd for digital i/o circuitry. 60 pmrxc i/o 5 reserved for mlu. no connect. 61 pmrxdv ipd/o 5 reserved for mlu. no connect. 62 pmrxd3 ipd/o 5 reserved for mlu. strap option: pd (default) = enable flow control. pu = disable flow control.
micrel, inc. KSZ8895MLU october 2011 11 m9999-100311-1.1 pin description (continued) pin number pin name type (1) port pin function (2) 63 pmrxd2 ipd/o 5 reserved for mlu. strap option: pd (default) = disable back pressure. pu = enable back pressure. 64 pmrxd1 ipd/o 5 reserved for mlu. strap option: pd (default) = drop excessive collision packets. pu = does not drop excessive collision packets. 65 pmrxd0 ipd/o 5 reserved for mlu. strap option: pd (default) = disable aggressive back-off algorithm in half-duplex mode. pu = enable for performance enhancement. 66 pmrxer ipd/o 5 reserved for mlu. strap option: pd (default) = 1522/1518 bytes; pu = packet size up to 1536 bytes. 67 pcrs ipd/o 5 reserved for mlu. strap option for port 4 only. pd (default) = force half -duplex if auto-negotiation is disabled or fails. pu = force full-duplex if auto negotiation is disabled or fails. refer to register 76. 68 pcol ipd/o 5 reserved for mlu. strap option for port 4 only. pd (default) = no force flow control, normal operation. pu = force flow control. refer to register 66. 69 smtxen ipd port 5 switch mii transmit enable. 70 smtxd3 ipd port 5 switch mii transmit bit 3. 71 smtxd2 ipd port 5 switch mii transmit bit 2. 72 smtxd1 ipd port 5 switch mii transmit bit 1. 73 smtxd0 ipd port 5 switch mii transmit bit 0. 74 smtxer ipd port 5 switch mii transmit error. 75 smtxc i/o port 5 switch mii transmit clock: input: sw5-mii mac mode. output: sw5-mii phy modes. 76 gndd gnd digital ground. 77 vddio p 3.3v, 2.5v or 1.8v digital v dd for digital i/o circuitry. 78 smrxc i/o port 5 switch mii receive clock: input: sw5-mii mac mode. output: sw5-mii phy mode. 79 smrxdv ipd/o switch m ii receive data valid. 80 smrxd3 ipd/o port 5 switch mii receive bit 3. strap option: pd (default) = disable switch sw5-mii full-duplex flow control pu = enable switch sw5-mii full-duplex flow control.
micrel, inc. KSZ8895MLU october 2011 12 m9999-100311-1.1 pin description (continued) pin number pin name type (1) port pin function (2) 81 smrxd2 ipd/o port 5 switch mii receive bit 2. strap option: pd (default) = switch sw5-mii in full-duplex mode; pu = switch sw5-mii in half-duplex mode. 82 smrxd1 ipd/o port 5 switch mii receive bit 1. strap option: pd (default) =port 5 switch sw5-mii in 100mbps mode; sw5-tmii in 200mbps mode. pu = switch sw5-m ii in 10mbps mode. port 5 switch mii receive bit 0. strap option: led mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0, link at 100/full ledx[2,1,0]=0,0,0 100/half ledx[2,1,0]=0,1,0 10/full ledx[2,1,0]=0,0,1 10/half ledx[2,1,0]=0,1,1 mode 1, link at 100/full ledx[2,1,0]=0,1,0 100/half ledx[2,1,0]=0,1,1 10/full ledx[2,1,0]=1,0,0 10/half ledx[2,1,0]=1,0,1 mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act 83 smrxd0 ipd/o ledx_0 speed full duplex 84 scol ipd/o port 5 switch mii collision detect: input: sw5-mii mac modes. output: sw5-mii phy modes. 85 scrs ipd/o port 5 switch mii modes carrier sense: input: sw5-mii mac modes. output: sw5-mii phy modes. 86 sconf1 ipd pin 91,86,87 are dual mii c onfiguration pins for the port5 mac5 mii. sw5-mii supports both mac mode and phy modes. pin#: (91, 86, 87) port5 switch mac5 sw5- mii 000 disable, otri 001 phy mode mii 010 mac mode mii 011 phy mode sni 100 disable (default) 101 phy mode mii 110 mac mode mii 111 phy mode sni 87 sconf0 ipd dual mii configuration pin. see pin 86 descriptions. 88 gndd gnd digital ground. 89 vddc p 1.2v digital core v dd . 90 led5-2 ipd/o 5 reserved for mlu strap option: aging setup. see ?aging? section. pu (default) = aging enable pd = aging disable.
micrel, inc. KSZ8895MLU october 2011 13 m9999-100311-1.1 pin description (continued) pin number pin name type (1) port pin function (2) 91 led5-1 ipu/o 5 reserved for mlu strap option: pu (default): enable phy[5] mii i/f. pd: tristate and disable all phy[5] mii output. (design should pull this pin down as default for mlu. 92 led5-0 ipu/o 5 reserved for mlu strap option for port 4 only. pu (default) = enable auto-negotiation. pd = disable auto-negotiation. strap to register76 bit[7]. 93 led4-2 ipu/o 4 led indicator 2. 94 led4-1 ipu/o 4 led indicator 1. 95 led4-0 ipu/o 4 led indicator 0. strap option: pu (default) = normal mode. pd = energy detection mode (edpd mode). strap to register 14 bits[4:3] 96 led3-2 ipu/o 3 led indicator 2. 97 led3-1 ipu/o 3 led indicator 1. 98 led3-0 ipu/o 3 led indicator 0. strap option: pu (default) = select i/o drive strength (8ma); pd = select i/o drive strength (12ma). strap to register132 bit[7-6]. 99 gndd gnd digital ground. 100 vddio p 3.3v, 2.5v or 1.8v digital v dd for digital i/o circuitry. 101 led2-2 ipu/o 2 led indicator 2. 102 led2-1 ipu/o 2 led indicator 1. strap option: for port 3 only. pu (default) = enable auto-negotiation. pd = disable auto-negotiation. strap to register60 bit[7]. 103 led2-0 ipu/o 2 led indicator 0. 104 led1-2 ipu/o 1 led indicator 2. 105 led1-1 ipu/o 1 led indicator 1. strap option: for port 3 only. pu (default) = no force flow control, normal operation. pd = force flow control. strap to register60 bit[4]. 106 led1-0 ipu/o 1 led indicator 0. strap option for port 3 only. pu (default) = force half -duplex if auto-negotiation is disabled or fails. pd = force full-duplex if auto negotiation is disabled or fails. strap to register60 bit[5]. 107 mdc ipu all switch mii management dat a clock. or smi interface clock. 108 mdio ipu/o all switch mii management data i/o. or smi interface data i/o. features internal pull down to define pin state when not driven. need an external pull-up when driven. 109 spiq ipu/o all spi serial data output in spi slave mode. 110 spic/scl ipu/o all spi slave mode: clock input (1) input clock up to 25mhz in spi slave mode, (2) output clock at 61khz in i 2 c master mode. see ?pin 113.?
micrel, inc. KSZ8895MLU october 2011 14 m9999-100311-1.1 pin description (continued) pin number pin name type (1) port pin function (2) 111 sspid/sda ipu/o all spi slave mode: se rial data input. (1) serial data input in spi slave mode; (2) serial data input/output in i 2 c master mode. see ?pin 113.? 112 spis_n ipu all spi slave mode: chip select (active low). (1) spi data transfer start in spi sl ave mode. when spis_n is high, the KSZ8895MLU is deselected and spiq is held in high impedance state, a high-to-low transition to initiate the spi data transfer. (2) not used in i 2 c master mode. serial bus configuration pin. for this case, if the eeprom is not pr esent, the KSZ8895MLU will start itself with the ps[1.0] = 00 default register values. pin configuration serial bus configuration ps[1.0]=00 i 2 c master mode for eeprom ps[1.0]=01 smi interface mode ps[1.0]=10 spi slave mode for cpu interface 113 ps1 ipd ps[1.0]=11 factory test mode (bist) 114 ps0 ipd serial bus configuration pin. see ?pin 113.? 115 rst_n ipu reset the KSZ8895MLU device. active low. 116 gndd gnd digital ground. 117 vddc p 1.2v digital core v dd . 118 testen ipd nc for normal oper ation. factory test pin. 119 scanen ipd nc for normal oper ation. factory test pin. 120 nc nc no connect. 121 x1 i 25mhz crystal clock connection/or 3.3v oscillator input. crystal/oscillator should be 50ppm tolerance. 122 x2 o 25mhz crystal clock connection. 123 nc nc no connect. 124 nc nc no connect. 125 ldo_o p when pin126 is pull-up, the internal 1.2v ldo controller is enabled and creates 1.2v output with using an external fet. when pin126 is pull-down (default), the pin 125 is tristated. 126 in_pwr_sel ipd pull-up to enable ldo_o of pin 125. pull-down to disable ldo_0. 127 gnda gnd analog ground. 128 test2 nc nc for normal operation. factory test pin. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down. otri = output tristated.
micrel, inc. KSZ8895MLU october 2011 15 m9999-100311-1.1 pin for strap-in options the KSZ8895MLU can function as a managed switch or unman aged switch. if no eeprom or micro-controller exists, the KSZ8895MLU will operate from its default setting. the strap-in option pins can be configures by external pull-up/down resistors and take the effect after power-down reset or warm reset, the functions are described in the following tables. pin number pin name pu/pd (1) description (1) 1 mdi-xdis ipd disable auto mdi/mdi-x. pd = (default) = normal operation pu = disable auto mdi/mdi-x on all ports. 62 pmrxd3 ipd/o strap option: pd (default) = enable flow control; pu = disable flow control. 63 pmrxd2 ipd/o strap option: pd (default) = disable back pressure; pu = enable back pressure. 64 pmrxd1 ipd/o strap option: pd (default) = drop excessive collision packets; pu = does not drop excessive collision packets. 65 pmrxd0 ipd/o strap option: pd (default) = disable aggressive back-off algorithm in half-duplex mode; pu = enable for performance enhancement. 66 pmrxer ipd/o strap option: pd (default) = 1522/1518 bytes; pu = packet size up to 1536 bytes. 67 pcrs ipd/o strap option for port 4 only. pd (default) = force half -duplex if auto-negotiation is disabled or fails. pu = force full-duplex if auto-negotiation is disabled or fails. refer to register 76. 68 pcol ipd/o strap option for port 4 only. pd (default) = no force flow control. pu = force flow control. refer to register 66. 80 smrxd3 ipd/o switch mii receive bit 3. strap option: pd (default) = disable switch sw5-mii full-duplex flow control; pu = enable switch sw5-mii full-duplex flow control. 81 smrxd2 ipd/o switch mii receive bit 2. strap option: pd (default) = switch sw5-mii in full-duplex mode; pu = switch sw5-mii in half-duplex mode. 82 smrxd1 ipd/o switch mii receive bit 1. strap option: pd (default) = switch sw5-mii in 100mbps mode and sw5-tmii in 200mbps pu = switch mii in 10mbps mode. switch mii receive bit 0. strap option: le d mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act 83 smrxd0 ipd/o ledx_0 speed fulld
micrel, inc. KSZ8895MLU october 2011 16 m9999-100311-1.1 pin for strap-in options (continued) pin number pin name pu/pd (1) description (1) 86 sconf1 ipd pins 91, 86, 87 are dual mii c onfiguration pins fo r the port5 mac5 mii. sw5-mii supports both mac mode and phy modes. pin#: (91, 86, 87) port5 switch mac5 sw5- mii 000 disable, otri 001 phy mode mii 010 mac mode mii 011 phy mode sni 100 disable 101 phy mode mii 110 mac mode mii 111 phy mode sni 87 sconf0 ipd dual mii configuration pin. see pin 86 descriptions. 90 led5-2 ipu/o strap option: aging setup. see ?aging? section pu (default) = aging enable; pd = aging disable. 91 led5-1 ipu/o strap option: pu (default): enable phy[5] mii i/f. pd: tristate all phy[5] mii out put. see ?pin 86 sconf1.? 92 led5-0 ipu/o strap option for port 4 only. pu (default) = enable auto-negotiation. pd = disable auto-negotiation. strap to register76 bit[7] 95 led4-0 ipu/o led indicator 0. strap option: pu (default) = normal mode. pd = energy detection mode (edpd mode). strap to register 14 bits[4:3] 98 led3-0 ipu/o led3 indicator 0. strap option: pu (default) = select i/o curr ent drive strength (8ma); pd = select i/o current drive strength (12ma). strap to register132 bit[7:6]. 101 led2-2 ipu/o led2 indicator 2. 102 led2-1 ipu/o led2 indicator 1. strap option for port 3 only. pu (default) = enable auto-negotiation. pd = disable auto-negotiation. strap to register60 bit[7] 103 led2-0 ipu/o led2 indicator 0. 104 led1-2 ipu/o led1 indicator 2. 105 led1-1 ipu/o led1 indicator 1. strap option for port 3 only. pu (default) = no force flow control, normal operation. pd = force flow control. strap to register50 bit[4]
micrel, inc. KSZ8895MLU october 2011 17 m9999-100311-1.1 pin for strap-in options (continued) pin number pin name pu/pd (2) description (2) 106 led1-0 ipu/o led1 indicator 0. strap option for port 3 only. pu (default) = force half -duplex if auto-negotiation is disabled or fails. pd = force full-duplex if auto negotiation is disabled or fails. strap to register60 bit[5]. serial bus configuration pin. for this case, if the eeprom is not present, the KSZ8895MLU will start itself with the ps[1:0] = 00 default register values. pin configuration serial bus configuration ps[1:0]=00 i 2 c master mode for eeprom ps[1:0]=01 smi interface mode ps[1:0]=10 spi slave mode for cpu interface 113 ps1 ipd ps[1:0]=11 factory test mode (bist) 114 ps0 ipd serial bus configuration pin. see ?pin 113.? 128 test2 nc nc for normal operation. factory test pin. notes: nc = no connect. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise.
micrel, inc. KSZ8895MLU october 2011 18 m9999-100311-1.1 introduction the KSZ8895MLU contains four 10/100 physical layer transcei vers and five media access control (mac) units with an integrated layer 2 managed switch. the device runs in two mo des. the first mode is as a 4-port integrated switch. the second is as a 4-port switch with the fifth mac. in th is mode, access to the fifth mac is provided through a media independent interface (mii). the KSZ8895MLU has the flexibility to reside in a managed or unmanaged design. in a managed design, a host processor has complete control of the KSZ8895MLU via the spi bus, or via the mdc/mdio interface with smi mode. an unmanaged design is achieved through i/o strappi ng or eeprom programming at system reset time. on the media side, the KSZ8895MLU supports ieee 802.3 10base-t, 100base-tx on all ports with auto mdi/mdix. the KSZ8895MLU can be used as fully-managed 4-port stand al one switch or hook up to microprocessor by its sw-mii interface for an application solution. physical signal transmission and reception are enhanced th rough the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. there are a number of major enhancements from t he ks8995ma to the KSZ8895MLU. these include: more host interface options, four queues prioritization, tag as well as port based vlan, rapid spanning tree support, igmp snooping support, port mirroring support and more flexible rate limiting and filtering functionality. physical layer transceiver 100base-tx transmit the 100base-tx transmit function performs parallel-to-seria l conversion, 4b/5b coding , scrambling, nrz-to-nrzi conversion, mlt3 encoding and transmission. the circuit starts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding followed by a scrambler. the serialized dat a is further converted from nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 1% 12.4k ? resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output is also incorporated in to the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function performs adaptive equalizat ion, dc restoration, mlt3-t o-nrzi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalization filter to compensate for inter- symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of th e length of the cable, the equalizer has to adjust its characteristics to optimize the performance. in this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cabl e characteristics, then tunes itself for optimization. this is an ongoing process and can self-adjust against envir onmental changes such as temperature variations. the equalized signal then goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and improv e the dynamic range. the differ ential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 1 25mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. the signal is then sent through the de-sc rambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to th e mii format and provided as the input data to the mac. pll clock synthesizer the KSZ8895MLU generates 125mhz, 83mhz, 41mhz, 25mhz a nd 10mhz clocks for system timing. internal clocks are generated from an external 25mhz crystal or oscillator. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectr um of the signal in order to reduce emi and baseline wander. the data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). this can generate a 2047- bit non-repetitive sequence. the receiver will then de-scramble t he incoming data stream with the same sequence at the transmitter.
micrel, inc. KSZ8895MLU october 2011 19 m9999-100311-1.1 10base-t transmit the output 10base-t driver is incorporat ed into the 100base-t driver to allow transmission with t he same magnetics. they are internally wave-shaped and pre-emphasized into out puts with typical 2.3v amplitude. the harmonic contents are at least 27db below the fundamental when driv en by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffer and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a pll perform the decoding function. the manchester-encoded da ta stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulse widths in order to prevent noises at the rxp or rxm input from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the KSZ8895MLU decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. mdi/mdi-x auto crossover to eliminate the need for crossover cables between simila r devices, the KSZ8895MLU supports hp auto mdi/mdi-x and ieee 802.3u standard mdi/mdi-x auto crossove r. hp auto mdi/mdi-x is the default. the auto-sense function detects remote transmit and receive pai rs and correctly assigns transmit and receive pairs for the KSZ8895MLU device. this feature is extremely useful when e nd users are unaware of cable types, and also, saves on an additional uplink configuration connection. the auto-crossover feature can be disabled through the port control registers, or miim phy registers. the ieee 802.3u standard mdi and mdi-x definitions are highlighted in table 1: mdi mdi-x rj-45 pins signals rj-45 pins signals 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 1. mdi/mdi-x pin definitions straight cable a straight cable connects an mdi device to an mdi-x device, or an mdi-x device to an mdi device. figure 1 depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi-x).
micrel, inc. KSZ8895MLU october 2011 20 m9999-100311-1.1 figure 1. typical straight cable connection crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi-x devic e to another mdi-x device. figure 2 shows a typical crossover cable connection betwe en two switches or hubs (two mdi-x devices). figure 2. typical crossover cable connection
micrel, inc. KSZ8895MLU october 2011 21 m9999-100311-1.1 auto-negotiation the KSZ8895MLU conforms to the auto-negotiation protocol as described by the 802.3 committee. auto-negotiation allows unshielded twisted pair (utp) link partners to sele ct the highest common mode of operation. link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is commo n to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest. ? highest: 100base-tx, full-duplex ? high: 100base-tx, half-duplex ? low: 10base-t, full-duplex ? lowest: 10base-t, half-duplex if auto-negotiation is not supported or the KSZ8895MLU link partner is forced to bypass auto-negotiation, the KSZ8895MLU sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the KSZ8895MLU to establish link by listening for a fi xed signal protocol in the absence of auto-negotiation advertisement protocol. the auto-negotiation link-up process is shown in figure 3.
micrel, inc. KSZ8895MLU october 2011 22 m9999-100311-1.1 figure 3. auto-negotiation on-chip termination resistors the KSZ8895MLU reduces board cost and simplifies board layout by using on-chip termination resistors for all ports and the rx/tx differential pairs without the exte rnal termination resistors. the solution of the on chip termination and internal biasing will save about 50% power consumption compare with using external biasing and termination resistors, and the transformer will not consume power any more. internal 1.2v ldo controller the KSZ8895MLU reduces board cost and simp lifies board layout by integrating an inte rnal 1.2v ldo controller to drive a low cost mosfet to supply the 1.2v core powe r voltage for a single 3.3v power supply solution.
micrel, inc. KSZ8895MLU october 2011 23 m9999-100311-1.1 power management the KSZ8895MLU supports a full-chip hardware power-down mode. when pwrdn pin 47 (pin pwrdn =0) is activated low, the entire chip is powered down. if this pin is de-asserted, the chip w ill be internally reset. the KSZ8895MLU can also use multiple power level of 3.3v, 2. 5v or 1.8v for vddio to support different i/o voltage. the KSZ8895MLU supports enhanced power management feature in low power state with energy detection to ensure low-power dissipation during device idle periods. there are fi ve operation modes under the power management function which is controlled by the register 14 bit [4:3] and the port register control 13 bit 3 as shown below: ? register 14 bit [4:3] = 00 normal operation mode ? register 14 bit [4:3] = 01 energy detect mode ? register 14 bit [4:3] = 10 soft power down mode ? register 14 bit [4:3] = 11 power saving mode ? port register 29, 45, 61, 77, 93 control 13 bit 3 =1 are for the port based power-down mode table 2 indicates all internal function blocks status under four different power management operation modes. power management operation modes KSZ8895MLU function blocks normal mode power-saving mode energy detect mode soft power-down mode internal pll clock enabled enabled disabled disabled tx/rx phy enabled rx unused block disabled energy detect at rx disabled mac enabled enabled disabled disabled host interface enabled enabled disabled disabled table 2. internal function block status normal operation mode this is the default setting bit [4:3] =00 in register 14 a fter the chip power-up or hardware reset. when KSZ8895MLU is in this normal operation mode, all pll clocks are running, phy and mac are on and the host interface is ready for cpu read or write. during the normal operation mode, the host cpu can set the bit [4:3] in register 14 to transit the current normal operation mode to any one of the other three power management operation modes. energy detect mode the energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8895MLU is not connected to an active link partner. in this mode, the device will save more power based on the regular less power consumption. if the cable is not plugg ed, the KSZ8895MLU can automatically enter to a low power state, otherwise known as the energy detect mode. in this mode, ksz8895m lu will keep transmitting 120ns width pulses at 1 pulse/s rate. once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8895MLU can automatically power up to nor mal power state in energy detect mode. energy detect mode consists of two states, normal power state and low power state. while in low power state, the KSZ8895MLU reduces power consumption by disabling all circuitr y except the energy detect circ uitry of the receiver. the energy detect mode is entered by setting bit [4:3] =01 in r egister 14. when the KSZ8895MLU is in this mode, it will monitor the cable energy. if there is no energy on the cable fo r a time longer than pre-configured value at bit [7:0] go- sleep time in register 15, KSZ8895MLU will go into a low power state. when KSZ8895MLU is in low power state, it will keep monitoring the cable energy. once the energy is detected from the ca ble, KSZ8895MLU will enter normal power state. when KSZ8895MLU is at normal power state, it is able to transmit or receive packet from the cable.
micrel, inc. KSZ8895MLU october 2011 24 m9999-100311-1.1 soft power-down mode the soft power-down mode is entered by setting bit [4:3] =10 in register 14. when KSZ8895MLU is in this mode, all pll clocks are disabled, also all of phys and the macs are o ff. any dummy host access will wake -up this device from current soft power-down mode to normal operation mode and internal reset will be issued to make all internal registers go to the default values. power-saving mode the power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit [4:3] =11 in register 14. when KSZ8895MLU is in this mode, all pll clocks are enabled, mac is on, all internal registers value will not change, and host interface is ready for cpu read or write. in this mode, it mainly controls the phy transceiver on or off based on line status to achieve power saving. the ph y remains transmitting and only turns off the unused receiver block. once activity resumes due to plugging a cable or a ttempting by the far end to establish link, the KSZ8895MLU can automatically enabled the phy power up to nor mal power state from power saving mode. during this power-saving mode, the host cpu can set bit [4:3] in register 14 to transit the current power saving mode to any one of the other three power management operation modes. port-based power-down mode in addition, the KSZ8895MLU features a per-port power down mode. to save power, a phy port that is not in use can be powered down via the port registers control 13 bit3, or miim phy registers 0 bit11. switch core address look-up the internal look-up table stores mac addresses and their as sociated information. it contai ns a 1k unicast address table plus switching information. the KSZ8895MLU is guaranteed to learn 1k addresses and distinguishes itself from a hash- based look-up table, which depending on the operating environment and probabilit ies, may not guarantee the absolute number of addresses it can learn. learning the internal look-up engine updates its table with a new entry if the following conditions are met: ? the received packet?s source address ( sa) does not exist in the look-up table. ? the received packet is good; the packet has no receiving errors and is of legal length. the look-up engine inserts the qualified sa into the table, along with the port numbe r and time stamp. if the table is full, the last entry of the table is deleted fi rst to make room for the new entry. migration the internal look-up engine also monitors whether a station is moved. if this occurs, it updates the table accordingly. migration happens when the following conditions are met: ? the received packet?s sa is in the table but t he associated source port information is different. ? the received packet is good; the packet has no receiving errors and is of legal length. the look-up engine will updat e the existing record in the table with the new source port information. aging the look-up engine will update the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the look-up engine will remove the record from the table. the look-up engine constantly perfo rms the aging process and will continuously remove aging records. the aging period is 300 ? 75 seconds. this feature can be enabled or disabled through register 3 or by external pull-up or pull-down resistors on led[5][2]. see ?register 3? section.
micrel, inc. KSZ8895MLU october 2011 25 m9999-100311-1.1 forwarding the KSZ8895MLU will forward packets using an algorithm that is depicted in the following flowcharts. figure 6 shows stage one of the forwarding algorithm wher e the search engine looks up the vlan id, static table, and dynamic table for the destination address, and comes up with ?port to forward 1? (ptf1). ptf1 is t hen further modified by the spanning tree, igmp snooping, port mirroring, and port vlan processes to come up with ?port to forward 2? (ptf2), as shown in figure 7. this is where the packet will be sent. KSZ8895MLU will not forward the following packets: ? error packets. these include framing errors, fcs erro rs, alignment errors, and illegal size packet errors. ? 802.3x pause frames. the KSZ8895MLU will intercept t hese packets and perform the appropriate actions. ? ?local? packets. based on destination address (da) look-up. if the destination port from t he look-up table matches the port where the packet was from, the packet is defined as ?local.? switching engine the KSZ8895MLU features a high-performance switching engi ne to move data to and from the mac?s, packet buffers. it operates in store and forward mode, while the efficient switching mechanism r educes overall latency. the KSZ8895MLU has a 64kb internal frame buffer. this resource is shared betw een all five ports. there are a total of 512 buffers available. each buffer is sized at 128b. media access controller (mac) operation the KSZ8895MLU strictly abide s by ieee 802.3 standards to maximize compatibility. inter-packet gap (ipg) if a frame is successfully transmitted, the 96-bit time ipg is measured between the two consecutive mtxen. if the current packet is experiencing collision, the 96-bit time ipg is measured from mcrs and the next mtxen. backoff algorithm the KSZ8895MLU implements the ieee std. 802.3 binary exponential back-off algor ithm, and optional ?aggressive mode? back off. after 16 collisions, the packet w ill be optionally dropped depending on the chip configuration in register 3. see ?register 3.? late collision if a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. illegal frames the KSZ8895MLU discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in register 4. for special applications, the KSZ8895MLU can also be programmed to accept frames up to 1916 bytes in register 4. since the KSZ8895MLU supports vlan tags, t he maximum sizing is adjusted when these tags are present. flow control the KSZ8895MLU supports standard 802.3x flow cont rol frames on both transmit and receive sides. on the receive side, if the KSZ8895MLU receives a pause control frame, the KSZ8895MLU will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. during this period (being flow controlled), only flow control pack ets from the KSZ8895MLU will be transmitted. on the transmit side, the KSZ8895MLU has intelligent and effici ent ways to determine when to invoke flow control. the flow control is based on availability of the system resour ces, including available buffers, available transmit queues and available receive queues.
micrel, inc. KSZ8895MLU october 2011 26 m9999-100311-1.1 the KSZ8895MLU flow controls a port that has just receiv ed a packet if the destination port resource is busy. the KSZ8895MLU issues a flow control frame (xoff), containing the maximum pause time defined in ieee standard 802.3x. once the resource is freed up, the ksz 8895mlu sends out the other flow control frame (xon) with zero pause time to turn off the flow control (turn on transmission to the port). a hysteresis feature is also prov ided to prevent over-activation and deactivation of the flow control mechanism. the KSZ8895MLU flow controls all ports if the receive queue becomes full. figure 4. destination address look-up flow chart (stage 1)
micrel, inc. KSZ8895MLU october 2011 27 m9999-100311-1.1 figure 5. destination address resolution flow chart (stage 2) the KSZ8895MLU will not forward the following packets: 1. error packets ? these include framing errors, frame check sequence (fcs) errors, alignment errors, and illegal size packet errors. 2. ieee802.3x pause frames ? KSZ8895MLU intercepts these packets and perform s full duplex flow control accordingly. 3. "local" packets ? based on destination address (da) lo okup, if the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local."
micrel, inc. KSZ8895MLU october 2011 28 m9999-100311-1.1 half-duplex back pressure the KSZ8895MLU also provides a half-dupl ex back pressure option (note: this is not in ieee 802.3 standards). the activation and deactivation conditions are the same as the ones given for full-duplex mode. if back pressure is required, the KSZ8895MLU sends preambles to defer the other station's transmission (carri er sense deference). to avoid jabber and excessive deference as def ined in ieee 802.3 standard, after a certain pe riod of time, the KSZ8895MLU discontinues carrier sense but raises it quickly after it drops packets to i nhibit other transmissions. this short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stati ons in a carrier sense deferred state. if the port has packets to send during a back pressure situation, the carrier-sense-type back pr essure is interrupted and those packets are transmitted instead. if there areno more packets to send, carrier-sense-type back pressure becomes active again until switch resources are free. if a collisiono ccurs, the binary exponential backoff algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets.to ensure no packet loss in 10base-t or 100base-tx half-duplex modes, the user must enable the following: ? aggressive backoff (register 3, bit 0) ? no excessive collision dr op (register 4, bit 3) ? back pressure (register 4, bit 5) these bits are not set as the default be cause this is not the ieee standard. broadcast storm protection the KSZ8895MLU has an intelligent option to protect the swit ch system from receiving too many broadcast packets. broadcast packets are normally forwarded to all ports except the source por t and thus use too many switch resources (bandwidth and available space in transmit queues). the ksz 8895mlu has the option to include ?multicast packets? for storm control. the broadcast storm ra te parameters are programmed globally and can be enabled or disabled on a per port basis. the rate is based on a 50ms interval for 100b t and a 500ms interval for 10bt. at the beginning of each interval, the counter is cleared to zero and the rate-limit me chanism starts to count the number of bytes during the interval. the rate definition is described in registers 6 and 7. the def ault setting for registers 6 and 7 is 0x4a (74 decimal). this is equal to a rate of 1%, calculated as follows: 148,800 frames/sec 50ms/interval 1% = 74 frames/interval (approx.) = 0x4a mii interface operation the media independent interface (mii) is specified by the ieee 802.3 committee and provides a common interface between physical layer and mac layer devices. the KSZ8895MLU provides such interfaces on port 5. the sw5-mii interface is used to connect to the fifth mac. the mii interfaces contains two distinct groups of signals, one for transmission and the other for receiving. port 5 mac 5 sw5-mii interface table 3 shows two connection manners: 1. the first is an external mac connects to sw5-mii phy mode. 2. the second is an external phy connects to sw5-mii mac mode. please see the pins [91, 86, and 87] description for detail configuration for the mac mode and phy mode, sw5-mii works with 25mhz and 2.5mhz clock for 100base-tx and 10base-t.
micrel, inc. KSZ8895MLU october 2011 29 m9999-100311-1.1 KSZ8895MLU phy mode connection KSZ8895MLU mac mode connection external mac KSZ8895MLU sw5-mii signals type description external phy KSZ8895MLU sw5-mii signals type mtxen smtxen input transmit enable mtxen smrxdv output mtxer smtxer input transmit error mtxer not used not used mtxd3 smtxd[3] input transmit data bit 3 mtxd3 smrxd[3] output mtxd2 smtxd[2] input transmit data bit 2 mtxd2 smrxd[2] output mtxd1 smtxd[1] input transmit data bit 1 mtxd1 smrxd[1] output mtxd0 smtxd[0] input transmit data bit 0 mtxd0 smrxd[0] output mtxc smtxc output transmit clock mtxc smrxc input mcol scol output collision detection mcol scol input mcrs scrs output carrier sense mcrs scrs input mrxdv smrxdv output receive data valid mrxdv smtxen input mrxer not used output receive error mrxer smtxer input mrxd3 smrxd[3] output receive data bit 3 mrxd3 smtxd[3] input mrxd2 smrxd[2] output receive data bit 2 mrxd2 smtxd[2] input mrxd1 smrxd[1] output receive data bit 1 mrxd1 smtxd[1] input mrxd0 smrxd[0] output receive data bit 0 mrxd0 smtxd[0] input mrxc smrxc output receive clock mrxc smtxc input table 3. switch mac 5 mii/turbo mii signals the switch mii interface operates in either mac mode or phy mode for KSZ8895MLU. these interfaces are nibble-wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). additional signals on the transmit side indicate when data is valid or when an error occurs during transmiss ion. likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. for half-duplex operation there is a signal that indicates a collision has occurred during transmission. note that the signal mrxer is not provided on the mii-sw interface for phy mode operation and the signal mtxer is not provided on the mii-sw interface for mac mode operation. normally mrxer would indicate a receive error coming from the physical layer device. mtxer would indicate a tr ansmit error from the mac device. these signals are not appropriate for this configuration. for phy mode operation, if the device interfacing with the KSZ8895MLU has an mrxer pin, it should be tied low. for mac mode operation, if the device interfacing with the KSZ8895MLU has an mtxer pin, it should be tied low. sni interface operation the serial network interface (sni) is compatible with some controllers used for network layer protocol processing. this interface can be directly connected to these types of devices. the signals are divided into two groups, one for transmission and the other for reception. the signals involved are described in table 4.
micrel, inc. KSZ8895MLU october 2011 30 m9999-100311-1.1 sni signal description KSZ8895MLU signal txen transmit enable smtxen txd serial transmit data smtxd[0] txc transmit clock smtxc col collision detection scol crs carrier sense smrxdv rxd serial receive data smrxd[0] rxc receive clock smrxc table 4. sni signals this interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). an additional signal on the transmit side indicates when data is valid. likewise, the receive side has an indicator t hat conveys when the data is valid. for half-duplex operation there is a signal that indi cates a collision has occurred during transmission.
micrel, inc. KSZ8895MLU october 2011 31 m9999-100311-1.1 advanced functionality qos priority support the KSZ8895MLU provides quality of service (qos) for applications such as voip and video conferencing. the KSZ8895MLU offer 1/2/4 priority queues option per port by setting the port registers xxx c ontrol 9 bit1 and the port registers xxx control 0 bit0, the 1/2/4 queues split as follows, [port registers xxx control 9 bit1, contro l 0 bit0]=00 single output queue as default. [port registers xxx control 9 bit1, control 0 bit0]=01 egress port can be split into two priority transmit queues. [port registers xxx control 9 bit1, control 0 bit0]=10 egress port can be split into four priority transmit queues. the four priority transmit queues is a new feature in the KSZ8895MLU. the queue 3 is the highest priority queue and queue 0 is the lowest priority queue. the port registers xxx c ontrol 7 bit1 and the port registers xxx control 0 bit0 are used to enable split transmit queues for ports 1, 2, 3, 4 and 5, re spectively. if a port's transmit queue is not split, high priorit y and low priority packets have equal priority in the transmit queue. there is an additional option to either always deliver high pr iority packets first or use programmable weighted fair queuing for the four priority queues scale by th e port registers control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by their bit[6:0]. register 130 bit[7:6] prio_2q[1:0] is used when the 2 queue conf iguration is selected, these bits are used to map the 2-bit result of ieee 802.1p from the registers 128, 129 or tos/diffserv mapping from registers 144-159 (for 4 queues) into two queues mode with priority high or low. please see the descriptions of the register 130 bits [7:6] for detail. port-based priority with port-based priority, each ingress port is individually clas sified as a priority 0-3 receiving port. all packets received a t the priority 3 receiving port are marked as high priority and ar e sent to the high-priority tr ansmit queue if the corresponding transmit queue is split. the port registers control 0 bits [4:3] is used to enable port-based priority for ports 1, 2, 3, 4 and 5, respectively. 802.1p-based priority for 802.1p-based priority, the KSZ8895MLU examines the ingr ess (incoming) packets to determine whether they are tagged. if tagged, the 3-bit priority field in the vlan tag is retrieved and compared against the ?priority mapping? value, as specified by the registers 128 and 129, both r egister 128/129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3 priority levels. the ?priority mapping? value is programmable. the following figure illustrates how the 802.1p priori ty field is embedded in the 802.1q vlan tag. figure 6. 802.1p priority field format
micrel, inc. KSZ8895MLU october 2011 32 m9999-100311-1.1 802.1p-based priority is enabled by bit [5] of the port regist ers control 0 for ports 1, 2, 3, 4 and 5, respectively. the KSZ8895MLU provides the option to insert or remove the priority tagged frame's header at each individual egress port. this header, consisting of the 2 bytes vl an protocol id (vpid) and the 2-byte tag control information field (tci), is also referred to as the ieee 802.1q vlan tag. tag insertion is enabled by bit [2] of the port registers control 0 and t he port register control 8 to select which source port (ingress port) pvid can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respective ly. at the egress port, untagged packets are tagged with the ingress port?s default tag. the de fault tags are programmed in the port registers control 3 and control 4 for ports 1, 2, 3, 4 and 5, respectively. t he KSZ8895MLU will not add tags to already tagged packets. tag removal is enabled by bit [1] of the port registers control 0 for por ts 1, 2, 3, 4 and 5, respectively. at the egress port, tagged packets will have their 802.1q vlan tags remo ved. the KSZ8895MLU will not modify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a qos feature that allows the KSZ8895MLU to set the ?user priority ceiling? at any ingress port by the port register control 2 bit 7. if the ingress packet?s priority field has a higher priority value than the default tag?s priority field of the ingress port, the packet?s priority field is replac ed with the default tag?s priority field . diffserv-based priority diffserv-based priority uses the tos regi sters (registers 144 to 159) in the advanc ed control registers section. the tos priority control registers implement a fully decoded, 128-bi t differentiated services code point (dscp) register to determine packet priority from the 6-bit tos field in the ip header. when the most significant 6 bits of the tos field are fully decoded, the resu ltant of the 64 possibilities of ds cp decoded is compared with the corresponding bits in the dscp register to determine priority. spanning tree support port 5 is the designated port for spanning tree support. the other ports (port 1 ? port 4) can be configured in one of the five spanning tree states via ?transmit enable,? ?receive enable,? and ?learning disable? register setti ngs in registers 18, 34, 50, and 66 for ports 1, 2, 3, and 4, respectively. the following description shows the port setting and software ac tions taken for each of the five spanning tree states. disable state: the port should not forward or receive any packets. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static tabl e with ?overriding bit? set) and the processor should discard those packets. note : processor is connected to port 5 via mii interface. addr ess learning is disabled on the port in this state. blocking state: only packets to the proces sor are forwarded. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1" software action: the processor should not send any packets to the port(s) in this state. the processor should program the ?static mac table? with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should also be set so that the switch will forward those specific packets to the processor. address learni ng is disabled on the port in this state. listening state: only packets to and from the pr ocessor are forwarded. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1. "software action: the processor should prog ram the static mac table with the entrie s that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific pac kets to the processor. the processor may send packets to the port(s) in this state, s ee ?tail tagging mode? section for details. address learning is disabled on the port in this state. learning state: only packets to and from the pr ocessor are forwarded. learning is enabled. port setting: ?transmit enable = 0, re ceive enable = 0, learning disable = 0.? software action: the processor should program the static mac ta ble with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific pac kets to the processor. the processor may send packets to the port(s) in this state, s ee ?tail tagging mode? section for details. address learning is enabled on the port in this state. forwarding state: packets are forwarded and received normally. learning is enabled. port setting: ?transmit enable = 1, re ceive enable = 1, learning disable = 0.?
micrel, inc. KSZ8895MLU october 2011 33 m9999-100311-1.1 software action: the processor should program the static mac ta ble with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific pac kets to the processor. the processor may send packets to the port(s) in this state, s ee ?tail tagging mode? section for details. address learning is enabled on the port in this state. rapid spanning tree support there are three operational states of the discarding, l earning, and forwarding assigned to each port for rstp: discarding ports do not participate in the acti ve topology and do not learn mac addresses. discarding state: the state incl uds three states of the disabl e, blocking and listening of stp. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static tabl e with ?overriding bit? set) and the processor should discard those packets. when disable the port?s learning capability (learni ng disable=?1?), set the register 1 bit5 and bi4 will flush rapidly with the port related entries in the dynamic mac table and static mac table. note : processor is connected to port 5 via mii interface. addr ess learning is disabled on the port in this state. ports in learning states learn mac addresse s, but do not forward user traffic. learning state: only packets to and from the pr ocessor are forwarded. learning is enabled. port setting: ?transmit enable = 0, re ceive enable = 0, learning disable = 0.? software action: the processor should program the static mac ta ble with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific pac kets to the processor. the processor may send packets to the port(s) in this state, s ee ?tail tagging mode? section for details. address learning is enabled on the port in this state. ports in forwarding states fully participat e in both data forwarding and mac learning. forwarding state: packets are forwarded and received normally. learning is enabled. port setting: ?transmit enable = 1, re ceive enable = 1, learning disable = 0.? software action: the processor should program the static mac ta ble with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific pac kets to the processor. the processor may send packets to the port(s) in this state, s ee ?tail tagging mode? section for details. address learning is enabled on the port in this state. rstp uses only one type of bpdu called rs tp bpdus. they are similar to stp configuration bpdus with the exception of a type field set to ?version 2? for rstp and ?version 0? for stp, and a flag field carrying additional information. tail tagging mode the tail tag is only seen and used by the port 5 interface, which should be connected to a processor by sw5-mii interface. the one byte tail tagging is used to indicate the sour ce/destination port in port 5. only bit [3-0] are used for the destination in the tail tagging byte. other bits are not used . the tail tag feature is enabled by setting register 12. figure 7. tail tag frame format
micrel, inc. KSZ8895MLU october 2011 34 m9999-100311-1.1 ingress to port 5 (host ? > KSZ8895MLU) bit [3:0] destination 0,0,0,0 normal (address look up for destination) 0,0,0,1 port 1 (direct forward to port1) 0,0,1,0 port 2 (direct forward to port2) 0,1,0,0 port 3 (direct forward to port3) 1,0,0,0 port 4 (direct forward to port4) 1,1,1,1 port 1, 2,3 and 4 (dir ect forward to port 1,2,3,4,) bit [7:4] 0,0,0,0 queue 0 is used at destination port 0,0,0,1 queue 1 is used at destination port 0,0,1,0 queue 2 is used at destination port 0,0,1,1 queue 3 is used at destination port x, 1,x,x whatever send packets to specified port in bit[3:0] 1, x,x,x bit[6:0] will be ignored egress from port 5 (KSZ8895MLU ? > host) bit [1:0] source 0,0 port 1 (packets from port 1) 0,1 port 2 (packets from port 2) 1,0 port 3 (packets from port 3) 1,1 port 4 (packets from port 4) table 5. tail tag rules igmp support there are two parts involved to support t he internet group management protocol (igmp) in layer 2. the first part is igmp snooping, the second part is this igmp packet to be sent back to the subscribed port. describe them as follows. igmp snooping the KSZ8895MLU traps igmp packets and forwards them only to the processo r (port 5 sw5-mii/rmii). the igmp packets are identified as ip packets (e ither ethernet ip packets, or ieee 802.3 snap ip packets) with ip version = 0x4 and protocol version number = 0x2. set register 5 bit [6] to ?1? to enable igmp snooping. igmp send back to the subscribed port once the host responds the received igmp packet, the host should knows the original igmp ingress port and send back the igmp packet to this port only, otherwise this igmp packet will be bro adcasted to all port to downgrade the performance. enable the tail tag mode, the host will know the igmp packe t received port from tail tag bits [1:0] and can send back the response igmp packet to this subscribed port by setting the bits [3:0] in the tail tag. enable ?tail tag mode? by setting register 12 bit 1.
micrel, inc. KSZ8895MLU october 2011 35 m9999-100311-1.1 port mirroring support KSZ8895MLU supports ?port mirror? comprehensively as: ? ?receive only? mirror on a port all the packets received on t he port will be mirrored on the sniffer port. fo r example, port 1 is programmed to be ?rx sniff,? and port 5 is programmed to be t he ?sniffer port.? a packet, received on port 1, is destined to port 4 after the internal look-up. the KSZ8895MLU will forward the pac ket to both port 4 and port 5. KSZ8895MLU can optionally forward even ?bad? received packets to port 5. ? ?transmit only? mirror on a port all the packets transmitted on the port wi ll be mirrored on the sniffer port. for example, port 1 is programmed to be ?tx sniff,? and port 5 is programmed to be t he ?sniffer port.? a packet, received on any of the ports, is destined to port 1 after the internal look-up. the KSZ8895MLU will forward the packet to both ports 1 and 5. ? ?receive and transmit? mirror on two ports all the packets received on por t a and transmitted on port b will be mirrored on the sniffe r port. to turn on the ?and? feature, set register 5 bit 0 to 1. fo r example, port 1 is programmed to be ?rx sniff,? port 2 is programmed to be ?transmit sniff,? and port 5 is programmed to be the ?sniffe r port.? a packet, received on port 1, is destined to port 4 after the internal look-up. the KSZ8895MLU will forward the packet to port 4 only, since it does not meet the ?and? condition. a packet, received on port 1, is destined to por t 2 after the internal look-up. the KSZ8895MLU will forward the packet to both port 2 and port 5. multiple ports can be selected to be ?rx sniffed? or ?tx sniff ed.? and any port can be selected to be the ?sniffer port.? all these per port features can be selected through register 17. vlan support KSZ8895MLU supports 128 active vlans and 4096 possible vids specified in ieee 802.1q. KSZ8895MLU provides a 128-entry vlan table, which correspond to 4096 possible vids and converts to fid (7 bits) for address look-up max 128 active vlans. if a non-tagged or null-vid-tagged packet is re ceived, the ingress port vid is used for look-up when 802.1q is enabled by the global register 5 control 3 bit 7. in the vlan mode, the look-up process star ts from vlan table look-up to determine whether the vid is valid. if the vid is not valid , the packet will be dropped and its address will not be learned. if the vid is valid, fid is retrieved for further look-up by the static mac table or dynamic ma c table. fid+da is used to determine the destination port. the followed table describes th e difference actions at different situations of da and fid+da in the static mac t able and dynamic mac table after the vlan table finish a look-up action. fid+sa is used for learning purposes. the followed table also describes how to learning in the dynamic mac table when vlan table has done a look-up and the static mac table without a valid entry. da found in static mac table use fid flag? fid match? da+fid found in dynamic mac table action no don?t care don?t care no broadcast to the membership ports defined in the vlan table bit [11:7]. no don?t care don?t care yes send to the destination port defined in the dynamic mac table bit [57:55]. yes 0 don?t care don?t care send to the destination port(s) defined in the static mac table bit [52:48]. yes 1 no no broadcast to the membership ports defined in the vlan table bit [11:7]. yes 1 no yes send to the destination port defined in the dynamic mac table bit [57:55]. yes 1 yes don?t care send to the destination port(s) defined in the static mac table bit [52:48]. table 6. fid+da look-up in the vlan mode
micrel, inc. KSZ8895MLU october 2011 36 m9999-100311-1.1 sa+fid found in dynamic mac table action no the sa+fid will be learned into the dynamic table. yes time stamp will be updated. table 7. fid+sa look-up in the vlan mode advanced vlan features are also supported in KSZ8895MLU, such as ?vlan ingress filter ing? and ?discard non pvid? defined in bits [6:5] of the port register control 2. these features can be controlled on a port basis. rate limiting support the KSZ8895MLU provides a fine resolution hardware rate limit ing. the rate step is 64kbps when the rate limit is less than 1mbps rate for 100bt or 10bt. the rate step is 1mbps w hen the rate limit is more than 1mbps rate for 100bt or 10bt (refer to data rate selection table whic h follow the end of the port register queue 0 ? 3 ingress/egress limit control section). the rate limit is independently on the ?rec eive side? and on the ?transmit side? on a per port basis. for 10base-t, a rate setting above 10 mbps means the rate is not lim ited. on the receive side, t he data receive rate for each priority at each port can be limited by setting up ingress rate control registers. on the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up egress rate control registers. the size of each frame has options to include minimum ifg (inter frame gap) or preamble byte, in addition to the data field (from packet da to fcs). ingress rate limit for ingress rate limiting, KSZ8895MLU provides options to sele ctively choose frames from all types, multicast, broadcast, and flooded unicast frames by bits [3 ? 2] of the port rate limit control r egister. the KSZ8895MLU counts the data rate from those selected type of frames. packets are dropped at the ingress port wh en the data rate exceeds the specified rate limit or the flow control takes effect without packet dr opped when the ingress rate limit flow control is enabled by the port rate limit control register bit 4. the ingress rate limiti ng supports the port-based, 802. 1p and diffserv-based priorities , the port-based priority is fixed priority 0 ? 3 selection by bits [4 ? 3] of the port register co ntrol 0. the 802.1p and diffserv- based priority can be mapped to priority 0 ? 3 by default of the register 128 and 129. in the ingress rate limit, set register 135 global control 19 bit3 for queue-based rate limit to be enabled if use two queues or four queues mode, all related ingress ports and egress port should be sp itted to two queues or four queues m ode by the port registers control 9 and control 0. the four queues mode will use q0-q3 for priority 0- 3 by bit [6-0] of the port register ingress limit control 1 ? 4. the two queues mode will use q0-q1 for priority 0-1by bit [6-0] of the por t register ingress limit control 1 ? 2. the priority levels in the packets of the 802.1p and diffserv can be progra mmed to priority 0-3 by the register 128 and 129 for a re- mapping. egress rate limit for egress rate limiting, the leaky bucket algorithm is applied to each output priority queue for shaping output traffic. inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. the throughput of each output priority queue is limited by the egress rate specified by the dat a rate selection table followed the egress rate limit control registers. if any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. after the memory of the queue or the port is used up, packet dropping or flow control will be triggered. as a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specif ied egress rate. the egress rate limiting supports the port- based, 802.1p and diffserv-based priorities, t he port-based priority is fixed priority 0 ? 3 selection by bits [4 ? 3] of the port register control 0. the 802.1p and diffserv-ba sed priority can be mapped to priority 0 ? 3 by default of the register 128 and 129. in the egress rate limit, set register 135 global contro l 19 bit3 for queue-based rate limit to be enabled if use two queues or four queues mode, all related ingress ports and egress port should be spitted to two queues or four queues mode by the port registers control 9 and control 0. the four queues mode will use q0-q3 for priority 0 ? 3 by bit [6 ? 0] of the port register egress limit control 1 ? 4. the two queues mode will use q0 ? q1 for priority 0 ? 1by bit [6 ? 0] of the port register egress limit control 1 ? 2.
micrel, inc. KSZ8895MLU october 2011 37 m9999-100311-1.1 the priority levels in the packets of the 802. 1p and diffserv can be programmed to priority 0 ? 3 by the register 128 and 129 for a re-mapping. when egress rate limit just use one que ue per port for the eg ress port rate limit, the priority packets will be based on the data rate selection table with the rate limit exact number. if eg ress rate limit use more than one queue per port for the egress port rate limit, the highest priority packets will be bas ed on the data rate selection t able for the rate limit exact number, other lower pr iority packet rate will be limited bas ed on 8:4:2:1 (default) priority ratio based on the highest priorit y rate. the transmit queue priority ratio is programmable. to reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth. transmit queue ratio programming in transmit queues 0 ? 3 of the egress port, the default priority ratio is 8: 4:2:1, the priority ratio can be programmed by the port registers control 10, 11, 12 and 13. w hen the transmit rate exceed the ratio limit in the transmit queue, the transmit rate will be limited by the transmit queue 0 ? 3 ratio of the port register contro l 10, 11, 12 and 13. the highest priority queue will be no limited, other lower priority queues will be limited based on the transmit queue ratio. filtering for self-address, unknown unicast/multicast address and unknown vid packet/ip multicast enable self-address filtering, the unknow n unicast packet filtering and forwarding by the register 131 global control 15. enable unknown multicast packet filtering and forw arding by the register 132 global control 16. enable unknown vid packet filtering and forwar ding by the register 133 global control 17. enable unknown ip multicast packet filtering and forwarding by the register 134 global control 18. this function is very useful in prevent ing those kinds of packets that could deg rade the quality of the port in applications such as voice over internet protocol (voip) and the dais y chain connection to prevent packets into endless loop. configuration interface i 2 c master serial bus configuration if a 2-wire eeprom exists, the KSZ8895MLU can perform more advanced features like br oadcast storm protection and rate control. the eeprom should have the entire valid configur ation data from register 0 to register 255 defined in the ?memory map,? except the status regist ers. after reset, the KSZ8895MLU will start to read all 255 registers sequentially from the eeprom. the configuration access time (t prgm ) is less than 30ms as shown in figure 12. figure 8. KSZ8895MLU eeprom configuration timing diagram
micrel, inc. KSZ8895MLU october 2011 38 m9999-100311-1.1 to configure the KSZ8895MLU wi th a pre-configured eeprom use the following steps: 1. at the board level, connect pin 11 0 on the KSZ8895MLU to the scl pin on the eeprom. connect pin 111 on the KSZ8895MLU to the sda pin on the eeprom. 2. set the input signals ps[1:0] (pins 113 and 114, resp ectively) to ?00.? this puts the KSZ8895MLU serial bus configuration into i2c master mode. 3. be sure the board-level reset signal is connected to the KSZ8895MLU reset signal on pin 115 (rst_n). 4. program the contents of the eeprom be fore placing it on the board with the desired config uration data. note that the first byte in the eeprom must be ?95? and second byte of chip id mu st be ?00? for the loading to occur properly. if this value is not corr ect, all other data will be ignored. 5. place eeprom on the board and power up the board. as sert the active-low board level reset to rst_n on the KSZ8895MLU. after the reset is de-asserted, the ksz 8895mlu will begin reading configuration data from the eeprom. the configuratio n access time (tprgm) is less than 30ms. note : for proper operation, make sure that pin 47 (p wrdn_n) is not asserted during the reset operation. spi slave serial bus configuration the KSZ8895MLU can also act as an spi slave device. throug h the spi, the entire feature set can be enabled, including ?vlan,? ?igmp snooping,? ?mib c ounters,? etc. the external ma ster device can access any regi ster from register 0 to register 127 randomly. the system should configure a ll the desired settings before enabling the switch in the KSZ8895MLU. to enable the switch, write a "1" to register 1 bit 0. two standard spi commands are supported (00000011 fo r ?read data,? and 00000010 for ?write data?). to speed configuration time, the KSZ8895MLU also supports multiple reads or writes. after a byte is written to or read from the KSZ8895MLU, the internal address counter automatically increments if the spi slave select si gnal (spis_n) continues to be driven low. if spis_n is kept low after the first byte is read, the next byte at the next address will be shifted out on spiq. if spis_n is kept low after the firs t byte is written, bits on the master ou t slave input (spid) line will be written to the next address. asserting spis_ n high terminates a read or write operation. this means that the spis_n signal must be asserted high and then low again before issuing another command and address. the address counter wraps back to zero once it reaches the highest address . therefore the entire regist er set can be written to or read from by issuing a single command and address. the default spi clock speed is 12.5mhz. the KSZ8895MLU is able to support a spi bus up to 25m hz (set register 12 bit [5:4]=0x10). a high performance spi master is re commended to prevent internal counter overflow. to use the KSZ8895MLU spi: 1. at the board level, connect KSZ8895MLU pins as noted in table 8: KSZ8895MLU pin number KSZ8895MLU signal name microprocessor signal description 112 spis_n spi slave select 110 spic spi clock 111 spid master out slave input 109 spiq master in slave output table 8. spi connections
micrel, inc. KSZ8895MLU october 2011 39 m9999-100311-1.1 2. set the input signals ps[1:0] (pins 113 and 114, respective ly) to ?10? to set the serial configuration to spi slave mode. 3. power up the board and assert a reset signal. after reset wait 100s, the start switch bit in register 1 will be set to ?0?. configure the desired settings in the ksz8895m lu before setting the start register to ?1.' 4. write configuration to registers usin g a typical spi write data cycle as shown in figure 9 or spi multiple write as shown in figure 11. note that data input on spi d is registered on the rising edge of spic. 5. registers can be read and configuration can be verified with a typical spi read data cycle as shown in figure 10 or a multiple read as shown in figure 12. note that read data is registered out of spiq on the falling edge of spic. 6. after configuration is written and verified, write a ?1? to register 1 bit 0 to begin KSZ8895MLU switch operation. figure 9. spi write data cycle figure 10. spi read data cycle
micrel, inc. KSZ8895MLU october 2011 40 m9999-100311-1.1 figure 11. spi multiple write figure 12. spi multiple read
micrel, inc. KSZ8895MLU october 2011 41 m9999-100311-1.1 mii management interface (miim) the KSZ8895MLU supports the st andard ieee 802.3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows uppe r-layer devices to monitor and control the states of the KSZ8895MLU. an external device with mdc/mdio capability is used to read the phy status or configure the phy settings. further detail on the miim interface is found in clause 22.2.4.5 of the ieee 802.3u specification. the miim interface consists of the following: ? a physical connection that incorp orates the data line (pin 108 mdio) and the clock line (pin 107 mdc). ? a specific protocol that operates acro ss the aforementioned physical connection that allows an external controller to communicate with the KSZ8895MLU device. ? access to a set of eight 16-bit registers, consisting of 8 standard miim registers [0:5h ], 1d and 1f miim registers per port. the miim interface can operate up to a ma ximum clock speed of 10mhz mdc clock. table 9 depicts the mii management interface frame format. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 aaaaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 aaaaa rrrrr 10 dddddddd_dddddddd z table 9. mii management interface frame format the miim interface does not have access to all the confi guration registers in the KSZ8895MLU. it can only access the standard miim registers. see ?miim registers?. the spi in terface and mdc/mdio smi mode, on the other hand, can be used to access the entire KSZ8895MLU feature set. serial management interface (smi) the smi is the KSZ8895MLU non-standard miim interface that provides access to all KSZ8895MLU configuration registers. this interface allows an exter nal device with mdc/mdio interface to co mpletely monitor and control the states of the KSZ8895MLU. the smi interface consists of the following: a physical connection that incorporates the data line (mdio) and the clock line (mdc). a specific protocol that operates acro ss the aforementioned physical connection t hat allows an external controller to communicate with the KSZ8895MLU device. access all KSZ8895MLU configuration registers. register access include s the global, port and advanced control registers 0 ? 255 (0x00 ? 0xff), and indirect access to the standard m iim registers [0:5] and custom miim registers [29, 31]. the smi interface can operate up to a ma ximum clock speed of 10mhz mdc clock. table 10 depicts the smi frame format. preamble start of frame read/write op code phyad address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 rr11r rrrrr z0 0000_0000_dddd_dddd z write 32 1?s 01 01 rr11r rrrrr 10 xxxx_xxxx_dddd_dddd z table 10. serial management interface (smi) frame format
micrel, inc. KSZ8895MLU october 2011 42 m9999-100311-1.1 smi register read access is selected when op code is set to ?1 0? and bits [2:1] of the phy address is set to ?11?. the 8-bit register address is the co ncatenation of {phy address bits [4:3], phy addr ess bits [0], reg address bit [4:0]}. ta is turn-around bits. ta bits [1:0] are ?z0? means the processo r mdio pin is changed to input hi-z from output mode and the followed ?0? is the read response from device, as the switch co nfiguration registers are 8-bit wide, only the lower 8 bits of data bits [15:0] are used smi register write access is selected when op code is set to ?01? and bits [2:1] of the phy address is set to ?11?. the 8-bit register address is the concatenati on of {phy address bits [4:3], phy addres s bits [0], reg address bit [4:0]}. ta bits [1:0] are set to ?10?, as the switch configuration register s are 8-bit wide, only the lower 8 bits of data bits [15:0] are used. to access the KSZ8895MLU registers 0-255 (0x00 - 0xff), the following applies: phyad [4, 3, 0] and regad [4:0] are concatenated to form t he 8-bit address; that is, {phyad [4, 3, 0], regad [4:0]} = bits [7:0] of the 8-bit address. registers are 8 data bits wide. for read operat ion, data bits [15:8] are read back as zeroes. for write operation, data bits [15:8] are not defined, and hence can be set to either zeroes or ones. smi register access is the same as the miim register acce ss, except for the register access requirements presented in this section.
micrel, inc. KSZ8895MLU october 2011 43 m9999-100311-1.1 register description offset decimal hex description 0 ? 1 0x00-0x01 chip id registers 2 ? 13 0x02-0x0d global control registers 14 ? 15 0x0e-0x0f power down management control registers 16 ? 20 0x10-0x14 port 1 control registers 21 ? 23 0x15-0x17 port 1 reserved (factory test registers) 24 ? 31 0x18-0x1f port 1 control/status registers 32 ? 36 0x20-0x24 port 2 control registers 37 ? 39 0x25-0x27 port 2 reserved (factory test registers) 40 ? 47 0x28-0x2f port 2 control/status registers 48 ? 52 0x30-0x34 port 3 control registers 53 ? 55 0x35-0x37 port 3 reserved (factory test registers) 56 ? 63 0x38-0x3f port 3 control/status registers 64 ? 68 0x40-0x44 port 4 control registers 69 ? 71 0x45-0x47 port 4 reserved (factory test registers) 72 ? 79 0x48-0x4f port 4 control/status registers 80 ? 84 0x50-0x54 port 5 control registers 85 ? 87 0x55-0x57 port 5 reserved (factory test registers) 88 ? 95 0x58-0x5f port 5 control/status registers 96 ? 103 0x60-0x67 reserved (factory testing registers) 104 ? 109 0x68-0x6d mac address registers 110 ? 111 0x6e-0x6f indirect access control registers 112 ? 120 0x70-0x78 indirect data registers 121 ? 123 0x79-0x7b reserved (factory testing registers) 124 ? 125 0x7c-0x7d port interrupt registers 126 ? 127 0x7e-0x7f reserved (factory testing registers) 128 ? 135 0x80-0x87 global control registers 136 0x88 switch self test control register 137 ? 143 0x89-0x8f qm global control registers 144 ? 145 0x90-0x91 tos priority control registers 146 ? 159 0x92-0x9f tos priority control registers 160 ? 175 0xa0-0xaf reserved (factory testing registers) 176 ? 190 0xb0-0xbe port 1 control registers
micrel, inc. KSZ8895MLU october 2011 44 m9999-100311-1.1 register descrip tion (continued) offset decimal hex description 191 0xbf reserved (factory testing regist er): transmit queue remap base register 192 ? 206 0xc0-0xce port 2 control registers 207 0xcf reserved (factory testing register) 208 ? 222 0xd0-0xde port 3 control registers 223 0xdf reserved (factory testing register) 224 ? 238 0xe0-0xee port 4 control registers 239 0xef reserved (factory testing register) 240 ? 254 0xf0-0xfe port 5 control registers 255 0xff reserved (factory testing register)
micrel, inc. KSZ8895MLU october 2011 45 m9999-100311-1.1 global registers register 0 (0 ? 00): chip id0 address name description mode default 7 ? 0 family id ch ip family. ro 0 ? 95 register 1 (0 ? 01): chip id1 / start switch address name description mode default 7 ? 4 chip id based on each part number in ksz8895 family ro 0 ? 4 3 ? 1 revision id revision id ro 0 ? 0 0 start switch 1, start the chip when external pins (ps1, ps0) = (01) or (1,0) note : in (ps1, ps0) = (0,0) mode, the chip will start automatically, after tr ying to read the external eeprom. if eeprom does not exist, the chip will use default values for all internal registers. if eeprom is present, the contents in the eeprom will be checked. the switch will check: register 0 = 0 ? 95 register 1 [7:4] chip id = 00 if this check is ok, the contents in the eeprom will override chip register default values. chip will not start when external pins (ps1, ps0) = (1, 0) or (0, 1). note : (ps1, ps0) = (1, 1) fo r factory test only. 0, stop the switch function of the chip. r/w 0 register 2 (0 ? 02): global control 0 address name description mode default 7 new back-off enable new back-off algorithm designed for unh 1 = enable 0 = disable r/w 0 6 reserved reserved. ro 0 5 flush dynamic mac table flush the entire dynamic mac table for rstp 1 = trigger the flush dynamic mac table operation. this bit is self clear. 0 = normal operation note : all the entries associated with a port that has its learning capability being turned off (learning disable) will be flushed. if you want to flush the entire table, a ll ports learning capability must be turned off. r/w (sc) 0
micrel, inc. KSZ8895MLU october 2011 46 m9999-100311-1.1 global registers (continued) register 2 (0 ? 02): global control 0 address name description mode default 4 flush static mac table flush the matched entries in static mac table for rstp 1 = trigger the flush stat ic mac table operation. this bit is self clear 0 = normal operation note : the matched entry is defined as the entry whose forwarding ports field contains a single port and mac address with unicast. this port, in turn, has its learning capability being turned off (learning disable). per port, multiple entries can be qualified as matched entries. r/w (sc) 0 3 reserved n/a don?t change ro 1 2 reserved n/a don?t change ro 1 1 unh mode 1, the switch will drop packets with 0x8808 in t/l filed, or da = 01-80-c2-00-00-01. 0, the switch will drop pa ckets qualified as ?flow control? packets. r/w 0 0 link change age 1, link change from ?link? to ?no link? will cause fast aging ( ? 800s) to age address table faster. after an age cycle is complete, the age logic will return to normal (300 ? 75 seconds). note: if any port is unplugged, all addresses will be automatically aged out. r/w 0 register 3 (0 ? 03): global control 1 address name description mode default 7 pass all frames 1, switch all packets including bad ones. used solely for debugging purpose. works in conjunction with sniffer mode. r/w 0 6 2k byte packet support 1 = enable support 2k byte packet 0 = disable support 2k byte packet r/w 0 5 ieee 802.3x transmit flow control disable 0, will enable transmit flow control based on an result. 1, will not enable transmit flow control regardless of an result. r/w 0 pin pmrxd3 strap option. pd(0): enable tx flow control (default). pu(1): disable tx/rx flow control. note : spflc has internal pull- down.
micrel, inc. KSZ8895MLU october 2011 47 m9999-100311-1.1 global registers (continued) register 3 (0 ? 03): global control 1 address name description mode default 4 ieee 802.3x receive flow control disable 0, will enable receive flow control based on an result. 1, will not enable receive flow control regardless of an result. note : bit 5 and bit 4 default values are controlled by the same pin, but they can be programmed independently. r/w 0 pin pmrxd3 strap option. pd (0): enable rx flow control (default). pu(1): disable tx/rx flow control. note : spflc has internal pull- down. 3 frame length field check 1, will check frame le ngth field in the ieee packets. if the actual length does not match, the packet will be dropped (for l/t <1500). r/w 0 2 aging enable 1, enable age function in the chip. 0, disable aging function. r/w 1 pin led[5][2] strap option. pd(0): aging disable. pu(1): aging enable (default). note : led[5][2] has internal pull up. 1 fast age enable 1 = turn on fast age (800s). r/w 0 0 aggressive back off enable 1 = enable more aggressive back-off algorithm in half duplex mode to enhance performance. this is not an ieee standard. r/w 0 pin pmrxd0 strap option. pd(0): disable aggressive back off (default). pu(1): aggressive back off. note : sppe has internal pull down.
micrel, inc. KSZ8895MLU october 2011 48 m9999-100311-1.1 global registers (continued) register 4 (0 ? 04): global control 2 address name description mode default 7 unicast port-vlan mismatch discard this feature is used for port vlan (described in register 17, register 33...). 1, all packets can not cross vlan boundary. 0, unicast packets (excluding unknown/ multicast/broadcast) can cross vlan boundary. r/w 1 6 multicast storm protection disable 1, ?broadcast storm protection? does not include multicast packets. only da=ffffffffffff packets will be regulated. 0, ?broadcast storm protection? includes da = ffffffffffff and da [40] = 1 packets. r/w 1 5 back pressure mode 1, carrier sense based backpressure is selected. 0, collision based backpressure is selected. r/w 1 4 flow control and back pressure fair mode 1, fair mode is selected. in this mode, if a flow control port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. 0, in this mode, if a flow control port and a non- flow control port talk to the same destination port, the flow control port will be flow controlled. this may not be ?fair? to the flow control port. r/w 1 3 no excessive collision drop 1, the switch will not drop packets when 16 or more collisions occur. 0, the switch will drop packets when 16 or more collisions occur. r/w 0 pin pmrxd1 strap option. pd(0): (default ) drop excessive collision packets. pu(1): don?t drop excessive collision packets. note : spdecp has internal pull down. 2 huge packet support 1, will accept packet sizes up to 1916 bytes (inclusive). this bit setting will override setting from bit 1 of the same register. 0, the maximum packet size will be determined by bit 1 of this register. r/w 0
micrel, inc. KSZ8895MLU october 2011 49 m9999-100311-1.1 global registers (continued) register 4 (0 ? 04): global control 2 address name description mode default 1 legal maximum packet size check disable 1, will accept packet sizes up to 1536 bytes (inclusive). 0, 1522 bytes for tagged packets (not including packets with stpid from cpu to ports 1-4), 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. r/w 0 pin pmrxer strap option. pd(0): (default) 1518/1522 byte packets. pu(1): 1536 byte packets. note : sppsz has internal pull- down. 0 reserved n/a ro 0 register 5 (0 ? 05): global control 3 address name description mode default 7 802.1q vlan enable 1, 802.1q vlan mode is turned on. vlan table needs to set up before the operation. 0, 802.1q vlan is disabled. r/w 0 6 igmp snoop enable on switch sw5-mii interface 1, igmp snoop enabled. all the igmp packets will be forwarded to switch mii port. 0, igmp snoop disabled. r/w 0 5 enable direct mode on switch sw5-mii interface 1, direct mode on port 5. this is a special mode for the switch mii interface. using preamble before mrxdv to direct switch to forward packets, bypassing internal look-up. 0, normal operation. r/w 0 4 enable pre-tag on switch sw5-mii interface 1, packets forwarded to switch mii interface will be pre-tagged with the source port number (preamble before mrxdv). 0, normal operation. r/w 0 3 ? 2 reserved n/a ro 00 1 enable ?tag? mask 1, the last 5 digits in the vid field are used as a mask to determine which port(s) the packet should be forwarded to. 0, no tag masks. note : turn off the 802.1q vlan mode (reg0x5, bit 7 = 0) for this bit to work. r/w 0 0 sniff mode select 1, will do rx and tx sniff (both source port and destination port need to match). 0, will do rx or tx sniff (either source port or destination port needs to match). this is the mode used to implement rx only sniff. r/w 0
micrel, inc. KSZ8895MLU october 2011 50 m9999-100311-1.1 global registers (continued) register 6 (0 ? 07): global control 4 address name description mode default 7 switch sw5-mii back pressure enable 1, enable half-duplex back pressure on switch mii interface. 0, disable back pressure on switch mii interface. r/w 0 6 switch sw5-mii half-duplex mode 1, enable mii interface half-duplex mode. 0, enable mii interface full-duplex mode. r/w pin smrxd2 strap option. pd(0): (default) full-duplex mode. pu(1): half- duplex mode. note : smrxd2 has internal pull- down. 5 switch sw5-mii flow control enable 1, enable full-duplex flow control on switch mii interface. 0, disable full-duplex flow control on switch mii interface. r/w pin smrxd3 strap option. pd(0): (default) disable flow control. pu(1): enable flow control. note : smrxd3 has internal pull- down. 4 switch sw5-mii speed 1, the switch sw5-mii is in 10mbps mode. 0, the switch sw5-mii is in 100mbps mode. r/w pin smrxd1 strap option. pd(0): (default) enable 100mbps. pu(1): enable 10mbps. note : smrxd1 has internal pull- down. 3 null vid replacement 1, will replace null vid with port vid (12 bits). 0, no replacement for null vid. r/w 0 2 ? 0 broadcast storm protection rate bit [10:8] this along with the next register determines how many ?64 byte blocks? of packet data allowed on an input port in a preset per iod. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 000
micrel, inc. KSZ8895MLU october 2011 51 m9999-100311-1.1 global registers (continued) register 7 (0 ? 07): global control 5 address name description mode default 7 ? 0 broadcast storm protection rate bit [7:0] this along with the previous register determines how many ?64 byte blocks? of packet data are allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 0x4a (1) note: 1. 148,800 frames/sec ? 1% = 74 frames/interval (approx.) = 0 ? 4a. register 8 (0 ? 08): global control 6 address name description mode default 7 ? 0 factory testing reserved r/w 0 ? 24 register 9 (0 ? 09): global control 7 address name description mode default 7 ? 0 factory testing reserved r/w 0 ? 28 register 10 (0 ? 0a): global control 8 address name description mode default 7 ? 0 factory testing reserved r/w 0 ? 00 register 11 (0 ? 0b): global control 9 address name description mode default 7 reversed n/a don?t change ro 0 6 reserved n/a don?t change ro 0 5 reserved n/a don?t change ro 0 4 reserved n/a don?t change ro 0 3 phy power save 1 = disable phy power-save mode. 0 = enable phy power-save mode. r/w 0 2 reserved n/a don?t change ro 0
micrel, inc. KSZ8895MLU october 2011 52 m9999-100311-1.1 global registers (continued) register 11 (0 ? 0b): global control 9 address name description mode default 0 = led mode 0. 1 = led mode 1. mode 0, link at 100/full ledx[2,1,0]=0,0,0 100/half ledx[2,1,0]=0,1,0 10/full ledx[2,1,0]=0,0,1 10/half ledx[2,1,0]=0,1,1 mode 1, link at 100/full ledx[2,1,0]=0,1,0 100/half ledx[2,1,0]=0,1,1 10/full ledx[2,1,0]=1,0,0 10/half ledx[2,1,0]=1,0,1 (0=led on, 1=led off) mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act 1 led mode ledx_0 speed fulld r/w pin smrxd0 - strap option. pull- down(0): enabled led mode 0. pull- up(1): enabled led mode 1. note : smrxd0 has internal pull- down 0. 0 spi/smi read sampling clock edge select select the spi/smi clock edge for sampling spi/smi read data 1 = trigger by rising edge of spi/smi clock (for high speed spi about 25mhz and smi about 10mhz) 0 = trigger by falling edge of spi/smi clock r/w 0
micrel, inc. KSZ8895MLU october 2011 53 m9999-100311-1.1 global registers (continued) register 12 (0 ? 0c): global control 10 address name description mode default 7 reserved n/a don?t change ro 0 6 reserved n/a don?t change ro 1 5 ? 4 cpu interface clock select select the internal clock speed for spi, mdi interface: 00 = 41.67mhz (spi up to 6.25mhz, mdc up to 6mhz) 01 = 83.33mhz default (spi scl up to 12.5mhz, mdc up to 12mhz) 10 = 125mhz (for high-speed spi about 25mhz) 11 = reserved note : the internal clock speeds of 83.33 or 125mhz must be selected when the chip is set in turbo-mii mode. r/w 01 3 reserved n/a ro 00 2 reserved n/a don?t change ro 1 1 tail tag enable tail tag feature is applied for port 5 only. 1 = insert 1 byte of data right before fcs 0 = do not insert r/w 0 0 pass flow control packet 1 = switch will not filter 802.1x ?flow control? packets 0 = switch will filter 802.1x ?flow control? packets r/w 0 register 13 (0 ? 0d): global control 11 address name description mode default 7 ? 0 factory testing n/a don?t change ro 00000000
micrel, inc. KSZ8895MLU october 2011 54 m9999-100311-1.1 global registers (continued) register 14 (0 ? 0e): power-down management control 1 address name description mode default 7 reserved n/a don?t change ro 0 6 reserved n/a don?t change ro 0 5 pll power down pll power down: 1 = disable 0 = enable note : it takes the effect in the energy detect mode (edpd mode). r/w 0 4 ? 3 power management mode power management mode: 00 = normal mode (d0) 01 = energy detection mode (d2) 10 = soft power down mode (d3) 11 = power saving mode (d1) r/w 00 pin led[4][0] strap option. pd(0): select energy detection mode pu(1): (default) normal mode note : led[4][0] has internal pull- up. register 14 (0 ? 0e): power-down management control 1 address name description mode default 2 ? 1 reserved n/a don?t change r/w 00 0 reserved n/a don?t change ro 0 register 15 (0 ? 0f): power-down management control 2 address name description mode default 7 - 0 go_sleep_time[7:0] when the energy detect mode is on, this value is used to control the mini mum period that the no energy event has to be detected consecutively before the device enters t he low power state. the unit is 20 ms. the default of go_sleep time is 1.6 seconds (80dec x 20ms). r/w 01010000
micrel, inc. KSZ8895MLU october 2011 55 m9999-100311-1.1 port registers the following registers are used to enable features that are assigned on a per port basis. the register bit assignments are the same for all ports, but the address for each port is different, as indicated: register 16 (0 ? 10): port 1 control 0 register 32 (0 ? 20): port 2 control 0 register 48 (0 ? 30): port 3 control 0 register 64 (0 ? 40): port 4 control 0 register 80 (0 ? 50): port 5 control 0 address name description mode default 7 broadcast storm protection enable 1, enable broadcast storm protection for ingress packets on the port. 0, disable broadcast storm protection. r/w 0 6 diffserv priority classification enable 1, enable diffserv priority classification for ingress packets on port. 0, disable diffserv function. r/w 0 5 802.1p priority classification enable 1, enable 802.1p priority classification for ingress packets on port. 0, disable 802.1p. r/w 0 4 ? 3 port-based priority classification enable = 00, ingress packets on port will be classified as priority 0 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. = 01, ingress packets on port will be classified as priority 1 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. = 10, ingress packets on port will be classified as priority 2 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. = 11, ingress packets on port will be classified as priority 3 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. note : ?diffserv?, ?802.1p? and port priority can be enabled at the same time. the or?d result of 802.1p and dscp overwrites the port priority. r/w 00 2 tag insertion 1, when packets are output on the port, the switch will add 802.1q tags to packets without 802.1q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress port?s ?port vid.? 0, disable tag insertion. r/w 0 1 tag removal 1, when packets are output on the port, the switch will remove 802.1q tags from packets with 802.1q tags when received. the switch will not modify packets received without tags. 0, disable tag removal. r/w 0
micrel, inc. KSZ8895MLU october 2011 56 m9999-100311-1.1 port registers (continued) register 16 (0 ? 10): port 1 control 0 register 32 (0 ? 20): port 2 control 0 register 48 (0 ? 30): port 3 control 0 register 64 (0 ? 40): port 4 control 0 register 80 (0 ? 50): port 5 control 0 address name description mode default 0 two queues split enable this bit0 in the regist er16/32/48/64/80 should be combination with register177/193/209/225/241 bit 1 for port 1-5 will select the split of 1/2/4 queues: for port 1, [register177 bit 1, register16 bit 0] = [11], reserved [10], the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. [01], the port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. [00], single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. r/w 0 register 17 (0 ? 11): port 1 control 1 register 33 (0 ? 21): port 2 control 1 register 49 (0 ? 31): port 3 control 1 register 65 (0 ? 41): port 4 control 1 register 81 (0 ? 51): port 5 control 1 address name description mode default 7 sniffer port 1, port is designated as sniffer port and will transmit packets that are monitored. 0, port is a normal port. r/w 0 6 receive sniff 1, all the packets received on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port.? 0, no receive monitoring. r/w 0 5 transmit sniff 1, all the packets transmitted on t he port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port.? 0, no transmit monitoring. r/w 0 4 ? 0 port vlan membership define the port?s port vlan membersh ip. bit 4 stands for port 5, bit 3 for port 4...bit 0 for port 1. the por t can only communicate within the membership. a ?1? includes a port in the membership; a ?0? excludes a port from membership. r/w 0x1f
micrel, inc. KSZ8895MLU october 2011 57 m9999-100311-1.1 port registers (continued) register 18 (0 ? 12): port 1 control 2 register 34 (0 ? 22): port 2 control 2 register 50 (0 ? 32): port 3 control 2 register 66 (0 ? 42): port 4 control 2 register 82 (0 ? 52): port 5 control 2 address name description mode default 7 user priority ceiling 1, if packet ?s ?user priority field? is greater than the ?user priority field? in the port def ault tag register, replace the packet?s ?user priority field? with the ?user priority field? in the port default tag r egister control 3. 0, no replace packet?s priority filed with port default tag priority filed of the port register control 3 bit [7:5]. r/w 0 6 ingress vlan filtering. 1, the switch will discard packets whose vid port membership in vlan table bit[20:16] does not include the ingress port. 0, no ingress vlan filtering. r/w 0 5 discard non-pvid packets 1, the switch will discard packets whose vid does not match ingress port default vid. 0, no packets will be discarded. r/w 0
micrel, inc. KSZ8895MLU october 2011 58 m9999-100311-1.1 port registers (continued) register 18 (0 ? 12): port 1 control 2 register 34 (0 ? 22): port 2 control 2 register 50 (0 ? 32): port 3 control 2 register 66 (0 ? 42): port 4 control 2 register 82 (0 ? 52): port 5 control 2 address name description mode default 4 force flow control 1, will always enable rx and tx flow control on the port, regardless of an result. 0, the flow control is enabled based on an result (default) r/w 0 strap-in option led1_1/pcol for port 3/port 4 led1_1 default pull up (1): not force flow control; pcol default pull- down (0): not force flow control. led1_1 pull down (0): force flow control; pcol pull- up (1): force flow control. note : led1_1 has internal pull-up; pcol have internal pull-down . 3 back pressure enable 1, enable port half-duplex back pressure. 0, disable port half-duplex back pressure. r/w 0 pin pmrxd2 strap option. pull-down (0): disable back pressure. pull-up(1): enable back pressure. note : pmrxd2 has internal pull- down. 2 transmit enable 1, enable packet transmission on the port. 0, disable packet transmission on the port. r/w 1 1 receive enable 1, enable packet reception on the port. 0, disable packet reception on the port. r/w 1 0 learning disable 1, disable switch address learning capability. 0, enable switch address learning. r/w 0
micrel, inc. KSZ8895MLU october 2011 59 m9999-100311-1.1 port registers (continued) register 19 (0 ? 13): port 1 control 3 register 35 (0 ? 23): port 2 control 3 register 51 (0 ? 33): port 3 control 3 register 67 (0 ? 43): port 4 control 3 register 83 (0 ? 53): port 5 control 3 address name description mode default 7 ? 0 default tag [15:8] port?s default tag, containing: 7 ? 5: user priority bits 4: cfi bit 3 ? 0 : vid[11:8] r/w 0 register 20 (0 ? 14): port 1 control 4 register 36 (0 ? 24): port 2 control 4 register 52 (0 ? 34): port 3 control 4 register 68 (0 ? 44): port 4 control 4 register 84 (0 ? 54): port 5 control 4 address name description mode default 7 ? 0 default tag [7:0] default port 1?s tag, containing: 7 ? 0: vid[7:0] r/w 1 note: registers 19 and 20 (and those corresponding to other ports) se rve two purposes: (1) associated with the ingress untagged packe ts, and used for egress tagging; (2) default vid for the ingress untagged or null-vid-tagged packets, and used for address look up. register 87 (0 ? 57): reserved control register address name description mode default 7 ? 0 reserved n/a don?t change ro 0 ? 00
micrel, inc. KSZ8895MLU october 2011 60 m9999-100311-1.1 port registers (continued) register 25 (0 ? 19): port 1 status 0 register 41 (0 ? 29): port 2 status 0 register 57 (0 ? 39): port 3 status 0 register 73 (0 ? 49): port 4 status 0 register 89 (0 ? 59): reserved address name description mode default 7 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = micrel auto mdi/mdi-x mode r/w 1 6 factory testing reserved ro 0 5 polrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive ro 0 3 receive flow control enable 1 = receive flow control feature is active 0 = receive flow control feature is inactive ro 0 2 operation speed 1 = link speed is 100mbps 0 = link speed is 10mbps ro 0 1 operation duplex 1 = link duplex is full 0 = link duplex is half ro 0 0 reserved n/a ro 0 register 26 (0 ? 1a): port 1 phy spec ial control/status register 42 (0 ? 2a): port 2 phy spec ial control/status register 58 (0 ? 3a): port 3 phy spec ial control/status register 74 (0 ? 4a): port 4 phy spec ial control/status register 90 (0 ? 5a): reserved address name description mode default 7 ? 4 reserved n/a don?t change ro 0000 3 force_lnk 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power saving 0 = disable power saving r/w 0 1 remote loopback 1 = perform remote loopback, loopback on port 1 as follows: port 1 (reg. 26, bit 1 = ?1?) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1?s phy end: txp1/txm1 (port 1) setting reg. 42, 58, 74, 90, bit 1 = ?1? will perform remote loopback on port 2, 3, 4, 5. 0 = normal operation. r/w 0 0 reserved n/a don?t change ro 0
micrel, inc. KSZ8895MLU october 2011 61 m9999-100311-1.1 port registers (continued) register 27 (0 ? 1b): reserved register 43 (0 ? 2b): reserved register 59 (0 ? 3b): reserved register 75 (0 ? 4b): reserved register 91 (0 ? 5b): reserved address name description mode default 7 ? 0 reserved n/a don?t change ro 0x00 register 28 (0 ? 1c): port 1 control 5 register 44 (0 ? 2c): port 2 control 5 register 60 (0 ? 3c): port 3 control 5 register 76 (0 ? 4c): port 4 control 5 register 92 (0 ? 5c): reserved address name description mode default 7 disable auto- negotiation 1, disable auto-negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 0, auto-negotiation is on. note: the register bit value is the invert of the strap value at the pin. r/w 0 for port 3/port 4 only. invert of pins led[2][1]/led[5][0] strap option. pd(0): disable auto- negotiation. pu(1): enable auto- negotiation. note :led[2][1]/l ed[5][0] have internal pull up. 6 forced speed 1, forced 100bt if an is disabled (bit 7). 0, forced 10bt if an is disabled (bit 7). r/w 1 5 forced duplex 1, forced full-duplex if (1) an is disabled or (2) an is enabled but failed. 0, forced half-duplex if (1) an is disabled or (2) an is enabled but failed (default). r/w 0 for port 3/port 4 only. pins led1_0/pcrs strap option. 1. for force half-duplex: led1_0 pin pull-up(1) (default) pcrs pin pull-down (0) (default). 2. for force full-duplex: led1_0 pin pull-down(0). pcrs pull-up (1): note : led1_0 has internal pull-up; pcrs have internal pull down .
micrel, inc. KSZ8895MLU october 2011 62 m9999-100311-1.1 port registers (continued) register 28 (0 ? 1c): port 1 control 5 register 44 (0 ? 2c): port 2 control 5 register 60 (0 ? 3c): port 3 control 5 register 76 (0 ? 4c): port 4 control 5 register 92 (0 ? 5c): reserved address name description mode default 4 advertised flow control capability 1, advertise flow control capability. 0, suppress flow control capability from transmission to link partner. r/w 1 3 advertised 100bt full- duplex capability 1, advertise 100bt full-duplex capability. 0, suppress 100bt full-duplex capability from transmission to link partner. r/w 1 2 advertised 100bt half- duplex capability 1, advertise 100bt half-duplex capability. 0, suppress 100bt half-duplex capability from transmission to link partner. r/w 1 1 advertised 10bt full- duplex capability 1, advertise 10bt full-duplex capability. 0, suppress 10bt full-duplex capability from transmission to link partner. r/w 1 0 advertised 10bt half- duplex capability 1, advertise 10bt half-duplex capability. 0, suppress 10bt half-duplex capability from transmission to link partner. r/w 1 register 29 (0 ? 1d): port 1 control 6 register 45 (0 ? 2d): port 2 control 6 register 61 (0 ? 3d): port 3 control 6 register 77 (0 ? 4d): port 4 control 6 register 93 (0 ? 5d): reserved address name description mode default 7 led off 1, turn off all port?s leds (ledx_2, ledx_1, ledx_0, where ?x? is the port number). these pins will be driven high if this bit is set to one. 0, normal operation. r/w 0 6 txids 1, disable port?s transmitter. 0, normal operation. r/w 0 5 restart an 1, restart auto-negotiation. 0, normal operation. r/w (sc) 0 4 fx reserved n/a ro 0 3 power down 1, power down. 0, normal operation. r/w 0 2 disable auto mdi/mdi-x 1, disable auto mdi/mdi-x function. 0, enable auto mdi/mdi-x function. r/w 0 1 forced mdi 1, if auto mdi/mdi-x is dis abled, force phy into mdix mode. 0, mdi mode. r/w 0
micrel, inc. KSZ8895MLU october 2011 63 m9999-100311-1.1 port registers (continued) register 29 (0 ? 1d): port 1 control 6 register 45 (0 ? 2d): port 2 control 6 register 61 (0 ? 3d): port 3 control 6 register 77 (0 ? 4d): port 4 control 6 register 93 (0 ? 5d): reserved address name description mode default 0 mac loopback 1 = perform mac loopback, loop back path as follows: e.g. set port 1 mac loopback (reg. 29, bit 0 = ?1?), use port 2 as monitor port. the packets will transfer start: port 2 receiving (also can start to receive packets from port 3, 4, 5). loop-back: port 1?s mac. end: port 2 transmitting (also can end at port 3, 4, 5 respectively). setting reg. 45, 61, 77, 93, bit 0 = ?1? will perform mac loopback on port 2, 3, 4, 5 respectively. 0 = normal operation. r/w 0 register 30 (0 ? 1e): port 1 status 1 register 46 (0 ? 2e): port 2 status 1 register 62 (0 ? 3e): port 3 status 1 register 78 (0 ? 4e): port 4 status 1 register 94 (0 ? 5e): reserved address name description mode default 7 mdix status 1, mdix. 0, mdi. ro 0 6 an done 1, an done. 0, an not done. ro 0 5 link good 1, link good. 0, link not good. ro 0 4 partner flow control capability 1, link partner flow control capable. 0, link partner not flow control capable. ro 0 3 partner 100bt full- duplex capability 1, link partner 100bt full-duplex capable. 0, link partner not 100bt full-duplex capable. ro 0 2 partner 100bt half- duplex capability 1, link partner 100bt half-duplex capable. 0, link partner not 100bt half-duplex capable. ro 0 1 partner 10bt full-duplex capability 1, link partner 10bt full-duplex capable. 0, link partner not 10bt full-duplex capable. ro 0 0 partner 10bt half-duplex capability 1, link partner 10bt half-duplex capable. 0, link partner not 10bt half-duplex capable. ro 0
micrel, inc. KSZ8895MLU october 2011 64 m9999-100311-1.1 port registers (continued) register 31 (0 ? 1f): port 1 control 7 and status 2 register 47 (0 ? 2f): port 2 control 7 and status 2 register 63 (0 ? 3f): port 3 control 7 and status 2 register 79 (0 ? 4f): port 4 control 7 and status 2 register 95 (0 ? 5f): reserved address name description mode default 7 phy loopback 1 = perform phy loopback, loop back path as follows: e.g. set port 1 phy loopback (reg. 31, bit 7 = ?1?) use the port 2 as monitor port. the packets will transfer start: port 2 receiving (also can start from port 3, 4, 5). loopback: pmd/pma of port 1?s phy end: port 2 transmitting (also can end at port 3, 4, 5 respectively). setting reg. 47, 63, 79, 95, bit 7 = ?1? will perform phy loopback on port 2, 3, 4, 5 respectively. 0 = normal operation. r/w 0 6 reserved ro 0 5 phy isolate 1, electrical isolation of phy from mii and tx+/tx-. 0, normal operation. r/w 0 4 soft reset 1, phy soft reset. this bit is self clear. 0, normal operation. r/w (sc) 0 3 force link 1, force link in the phy. 0, normal operation r/w 0 2 ? 0 port operation mode indication indicate the current stat e of port operation mode: [000] = reserved [001] = still in auto-negotiation [010] = 10base-t half duplex [011] = 100base-tx/fx half duplex [100] = reserved [101] = 10base-t full duplex [110] = 100base-tx/fx full duplex [111] = reserved ro 001 note : port control 12 and 13, 14 and port status 1, 2 contents can be accessed by miim (mdc/mdio) interface via the standard miim reg ister definition.
micrel, inc. KSZ8895MLU october 2011 65 m9999-100311-1.1 advanced control registers registers 104 to 109 define the switching engine?s mac address . this 48-bit address is used as the source address in mac pause control frames. register 104 (0 ? 68): mac address register 0 address name description mode default 7 ? 0 maca[47:40] r/w 0x00 register 105 (0 ? 69): mac address register 1 address name description mode default 7 ? 0 maca[39:32] r/w 0x10 register 106 (0 ? 6a): mac address register 2 address name description mode default 7 ? 0 maca[31:24] r/w 0xa1 register 107 (0 ? 6b): mac address register 3 address name description mode default 7 ? 0 maca[23:16] r/w 0xff register 108 (0 ? 6c): mac address register 4 address name description mode default 7 ? 0 maca[15:8] r/w 0xff register 109 (0 ? 6d): mac address register 5 address name description mode default 7 ? 0 maca[7:0] r/w 0xff
micrel, inc. KSZ8895MLU october 2011 66 m9999-100311-1.1 advanced control registers (continued) use registers 110 and 111 to read or write data to the static mac addres s table, vlan table, dynamic address table, or the mib counters. register 110 (0 ? 6e): indirect access control 0 address name description mode default 7 ? 5 reserved reserved. r/w 000 4 read high write low 1, read cycle. 0, write cycle. r/w 0 3 ? 2 table select 00 = static mac address table selected. 01 = vlan table selected. 10 = dynamic address table selected. 11 = mib counter selected. r/w 0 1 ? 0 indirect address high bit 9 ? 8 of indirect address. r/w 00 register 111 (0 ? 6f): indirect access control 1 address name description mode default 7 ? 0 indirect address low bit 7 ? 0 of indirect address. r/w 00000000 note : write to register 111 will actually trigger a command. read or write access will be decided by bit 4 of register 110. register 112 (0 ? 70): indirect data register 8 address name description mode default 68 ? 64 indirect data bit 68 ? 64 of indirect data. r/w 00000 register 113 (0 ? 71): indirect data register 7 address name description mode default 63 ? 56 indirect data bit 63 ? 56 of indirect data. r/w 00000000 register 114 (0 ? 72): indirect data register 6 address name description mode default 55 ? 48 indirect data bit 55 ? 48 of indirect data. r/w 00000000 register 115 (0 ? 73): indirect data register 5 address name description mode default 47 ? 40 indirect data bit 47 ? 40 of indirect data. r/w 00000000 register 116 (0 ? 74): indirect data register 4 address name description mode default 39 ? 32 indirect data bit 39 ? 32 of indirect data. r/w 00000000
micrel, inc. KSZ8895MLU october 2011 67 m9999-100311-1.1 advanced control registers (continued) use registers 110 and 111 to read or write data to the static mac addres s table, vlan table, dynamic address table, or the mib counters. register 117 (0 ? 75): indirect data register 3 address name description mode default 31 ? 24 indirect data bit of 31 ? 24 of indirect data r/w 00000000 register 118 (0 ? 76): indirect data register 2 address name description mode default 23 ? 16 indirect data bit 23 ? 16 of indirect data. r/w 00000000 register 119 (0 ? 77): indirect data register 1 address name description mode default 15 ? 8 indirect data bit 15 ? 8 of indirect data. r/w 00000000 register 120 (0 ? 78): indirect data register 0 address name description mode default 7 ? 0 indirect data bit 7 ? 0 of indirect data. r/w 00000000 register 124 (0x7c): interrupt status register address name description mode default 7 ? 5 reserved reserved ro 000 4 reserved reserved ro 0 3 port 4 interrupt status 1, port 4 interrupt request 0, normal note : this bit is set by port 4 link change. write a ?1? to clear this bit ro 0 2 port 3 interrupt status 1, port 3 interrupt request 0, normal note : this bit is set by port 3 link change. write a ?1? to clear this bit ro 0 1 port 2 interrupt status 1, port 2 interrupt request 0, normal note : this bit is set by port 2 link change. write a ?1? to clear this bit ro 0 0 port 1 interrupt status 1, port 1 interrupt request 0, normal note : this bit is set by port 1 link change. write a ?1? to clear this bit ro 0
micrel, inc. KSZ8895MLU october 2011 68 m9999-100311-1.1 advanced control registers (continued) use registers 110 and 111 to read or write data to the static mac addres s table, vlan table, dynamic address table, or the mib counters. register 125 (0x7d): interrupt mask register address name description mode default 7 ? 5 reserved reserved. ro 000 4 reserved reserved ro 0 3 port 4 interrupt mask 1, port 4 interrupt mask 0, normal r/w 0 2 port 3 interrupt mask 1, port 3 interrupt mask 0, normal r/w 0 1 port 2 interrupt mask 1, port 2 interrupt mask 0, normal r/w 0 0 port 1 interrupt mask 1, port 1 interrupt mask 0, normal r/w 0 the registers 128, 129 can be used to map fr om 802.1p priority field 0-7 to switch?s four priority queues 0-3, 0x3 is highest priority queues as priority 3, 0x0 is lo west priority queues as priority 0. register 128 (0x80): global control 12 address name description mode default 7 - 6 tag_0x3 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x3 r/w 0x1 5 - 4 tag_0x2 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x2 r/w 0x1 3 - 2 tag_0x1 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x1 r/w 0x0 1 - 0 tag_0x0 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x0 r/w 0x0 register 129 (0x81): global control 13 address name description mode default 7 - 6 tag_0x7 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x7 r/w 0x3 5 - 4 tag_0x6 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x6 r/w 0x3 3 - 2 tag_0x5 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x5 r/w 0x2 1 - 0 tag_0x4 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x4 r/w 0x2
micrel, inc. KSZ8895MLU october 2011 69 m9999-100311-1.1 advanced control registers (continued) register 130 (0x82): global control 14 address name description mode default 7 ? 6 pri_2q[1:0] (note that program prio_2q[1:0] = 01 is not supported and should be avoided) when the 2 queue configurat ion is selected, these pri_2q[1:0] bits are used to map the 2-bit result of ieee 802.1p from register 128/129 or tos/diffserv from register 144- 159 mapping (for 4 queues) into two queues low/high priorities. 2-bit result of ieee 802.1p or tos/diffserv 00 (0) = map to low priority queue 01 (1) = prio_2q[0] map to low/high priority queue 10 (2) = prio_2q[1] map to low/high priority queue 11 (3) = map to high priority queue pri_2q[1:0] = 00: result 0, 1, 2 are low priority. 3 is high priority. 10: result 0, 1 are low priority. 2, 3 are high priority (default). 11: result 0 is low priority. 1, 2, 3 are high priority. r/w 10 5 reserved n/a don?t change ro 0 4 reserved n/a don?t change ro 0 3 ? 2 reserved n/a don?t change ro 01 1 reserved n/a don?t change ro 0 0 reserved n/a don?t change ro 0. register 131 (0x83): global control 15 address name description mode default 7 reserved n/a ro 0 6 reserved n/a ro 0 5 unknown unicast packet forward 1 = enable supporting unknown unicast packet forward 0 = disable r/w 0 4 ? 0 unknown unicast packet forward port map 00000 = filter unknown unicast packet 00001 = forward unknown unicast packet to port 1 00011 = forward unknown unicast packet to port 1, port 2 ? 11111 = broadcast unknown unicast packet to all ports r/w 00000
micrel, inc. KSZ8895MLU october 2011 70 m9999-100311-1.1 advanced control registers (continued) register 132 (0x84): global control 16 address name description mode default 7 ? 6 chip i/o output drive strength select[1:0] output drive strength select[1:0] = 00 = 4ma drive strength 01 = 8ma drive strength (default) 10 = 12ma drive strength 11 = 16ma drive strength note : bit[1] value is the invert of the strap value at the pin. bit[0] value is the same of the strap value at the pin r/w pin led[3][0] strap option. pull- down (0): select 12ma drive strength. pull-up (1): select 8ma drive strength. note : led[3][0] has internal pull- up. 5 unknown multicast packet forward (not including ip multicast packet) 1 = enable supporting unknown multicast packet forward 0 = disable r/w 0 4 ? 0 unknown multicast packet forward port map 00000 = filter unknown multicast packet 00001 = forward unknown multicast packet to port 1 00011 = forward unknown multicast packet to port 1, port 2 ? 11111 = broadcast unknown multicast packet to all ports r/w 00000 register 133(0x85): global control 17 address name description mode default 7 - 6 reserved ro 00 5 unknown vid packet forward 1 = enable supporting unknown vid packet forward 0 = disable r/w 0 4 - 0 unknown vid packet forward port map 00000 = filter unknown vid packet 00001 = forward unknown vid packet to port 1 00011 = forward unknown vid packet to port 1, port 2 ? 11111 = broadcast unknown vid packet to all ports r/w 00000
micrel, inc. KSZ8895MLU october 2011 71 m9999-100311-1.1 advanced control registers (continued) register 134 (0x86): global control 18 address name description mode default 7 reserved n/a ro 0 6 self address filter enable 1 = enable filtering of self-address unicast and multicast packet 0 = do not filter self-address packet note : the self-address filterin g will filter packets on the egress port, self mac address is assigned in the register 104 ? 109. r/w 0 5 unknown ip multicast packet forward 1 = enable supporting unknown ip multicast packet forward 0 = disable r/w 0 4 ? 0 unknown ip multicast packet forward port map 00000 = filter unknown ip multicast packet 00001 = forward unknown ip multicast packet to port 1 00011 = forward unknown ip multicast packet to port 1, port 2 ? 11111 = broadcast unknown ip multicast packet to all ports r/w 00000 register 135 (0x87): global control 19 address name description mode default 7 reserved n/a don?t change ro 0 6 reserved n/a don?t change ro 0 5 ? 4 ingress rate limit period the unit period for calculating ingress rate limit 00 = 16 ms 01 = 64 ms 1x = 256 ms r/w 01 3 queue-based egress rate limit enabled enable queue-based egress rate limit 0 = port-base egress rate limit (default) 1 = queue-based egress rate limit r/w 0 2 insertion source port pvid tag selection enable 1 = enable source port pvid tag insertion or non- insertion option on the egress port for each source port pvid based on the ports registers control 8. 0 = disable, all packets from any ingress port will be inserted pvid based on port register control 0 bit 2. r/w 0 1 ? 0 reserved n/a don?t change ro 00
micrel, inc. KSZ8895MLU october 2011 72 m9999-100311-1.1 advanced control registers (continued) register 144 (0x90): tos priority control register 0 the ipv4/ipv6 tos priority control regist ers implement a fully decoded 64 bit different iated services code point (dscp) registe r used to determine priority from the 6 bit tos field in the ip header. the most si gnificant 6 bits of the tos fi eld are fully decoded into 64 poss ibilities, and the singular code that results is mapped to the value in the corresponding bit in the dscp register. address name description mode default 7 ? 6 dscp[7:6] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x0c r/w 00 5 ? 4 dscp[5:4] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x08 r/w 00 3 ? 2 dscp[3:2] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x04 r/w 00 1 ? 0 dscp[1:0] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x00 r/w 00 register 145 (0x91): tos priority control register 1 address name description mode default 7 ? 6 dscp[15:14] ipv4 and ipv6 mapping _ for value 0x1c r/w 00 5 ? 4 dscp[13:12] ipv4 and ipv6 mapping _ for value 0x18 r/w 00 3 ? 2 dscp[11:10] ipv4 and ipv6 mapping _ for value 0x14 r/w 00 1 ? 0 dscp[9:8] ipv4 and ipv6 mapping _ for value 0x10 r/w 00 register 146 (0x92): tos priority control register 2 address name description mode default 7 ? 6 dscp[23:22] ipv4 and ipv6 mapping _ for value 0x2c r/w 00 5 ? 4 dscp[21:20] ipv4 and ipv6 mapping _ for value 0x28 r/w 00 3 ? 2 dscp[19:18] ipv4 and ipv6 mapping _ for value 0x24 r/w 00 1 ? 0 dscp[17:16] ipv4 and ipv6 mapping _ for value 0x20 r/w 00 register 147 (0x93): tos priority control register 3 address name description mode default 7 ? 6 dscp[31:30] ipv4 and ipv6 mapping _ for value 0x3c r/w 00 5 ? 4 dscp[29:28] ipv4 and ipv6 mapping _ for value 0x38 r/w 00 3 ? 2 dscp[27:26] ipv4 and ipv6 mapping _ for value 0x34 r/w 00 1 ? 0 dscp[25:24] ipv4 and ipv6 mapping _ for value 0x30 r/w 00
micrel, inc. KSZ8895MLU october 2011 73 m9999-100311-1.1 advanced control registers (continued) register 148 (0x94): tos priority control register 4 address name description mode default 7 ? 6 dscp[39:38] ipv4 and ipv6 mapping _ for value 0x4c r/w 00 5 ? 4 dscp[37:36] ipv4 and ipv6 mapping _ for value 0x48 r/w 00 3 ? 2 dscp[35:34] ipv4 and ipv6 mapping _ for value 0x44 r/w 00 1 ? 0 dscp[33:32] ipv4 and ipv6 mapping _ for value 0x40 r/w 00 register 149 (0x95): tos priority control register 5 address name description mode default 7 ? 6 dscp[47:46] ipv4 and ipv6 mapping _ for value 0x5c r/w 00 5 ? 4 dscp[45:44] ipv4 and ipv6 mapping _ for value 0x58 r/w 00 3 ? 2 dscp[43:42] ipv4 and ipv6 mapping _ for value 0x54 r/w 00 1 ? 0 dscp[41:40] ipv4 and ipv6 mapping _ for value 0x50 r/w 00 register 150 (0x96): tos priority control register 6 address name description mode default 7 ? 6 dscp[55:54] ipv4 and ipv6 mapping _ for value 0x6c r/w 00 5 ? 4 dscp[53:52] ipv4 and ipv6 mapping _ for value 0x68 r/w 00 3 ? 2 dscp[51:50] ipv4 and ipv6 mapping _ for value 0x64 r/w 00 1 ? 0 dscp[49:48] ipv4 and ipv6 mapping _ for value 0x60 r/w 00 register 151 (0x97): tos priority control register 7 address name description mode default 7 ? 6 dscp[63:62] ipv4 and ipv6 mapping _ for value 0x7c r/w 00 5 ? 4 dscp[61:60] ipv4 and ipv6 mapping _ for value 0x78 r/w 00 3 ? 2 dscp[59:58] ipv4 and ipv6 mapping _ for value 0x74 r/w 00 1 ? 0 dscp[57:56] ipv4 and ipv6 mapping _ for value 0x70 r/w 00 register 152 (0x98): tos priority control register 8 address name description mode default 7 ? 6 dscp[71:70] ipv4 and ipv6 mapping _ for value 0x8c r/w 00 5 ? 4 dscp[69:68] ipv4 and ipv6 mapping _ for value 0x88 r/w 00 3 ? 2 dscp[67:66] ipv4 and ipv6 mapping _ for value 0x84 r/w 00 1 ? 0 dscp[65:64] ipv4 and ipv6 mapping _ for value 0x80 r/w 00
micrel, inc. KSZ8895MLU october 2011 74 m9999-100311-1.1 advanced control registers (continued) register 153 (0x99): tos priority control register 9 address name description mode default 7 ? 6 dscp[79:78] ipv4 and ipv6 mapping _ for value 0x9c r/w 00 5 ? 4 dscp[77:76] ipv4 and ipv6 mapping _ for value 0x98 r/w 00 3 ? 2 dscp[75:74] ipv4 and ipv6 mapping _ for value 0x94 r/w 00 1 ? 0 dscp[73:72] ipv4 and ipv6 mapping _ for value 0x90 r/w 00 register 154 (0x9a): tos priority control register 10 address name description mode default 7 ? 6 dscp[87:86] ipv4 and ipv6 mapping _ for value 0xac r/w 00 5 ? 4 dscp[85:84] ipv4 and ipv6 mapping _ for value 0xa8 r/w 00 3 ? 2 dscp[83:82] ipv4 and ipv6 mapping _ for value 0xa4 r/w 00 1 ? 0 dscp[81:80] ipv4 and ipv6 mapping _ for value 0xa0 r/w 00 register 155 (0x9b): tos priority control register 11 address name description mode default 7 ? 6 dscp[95:94] ipv4 and ipv6 mapping _ for value 0xbc r/w 00 5 ? 4 dscp[93:92] ipv4 and ipv6 mapping _ for value 0xb8 r/w 00 3 ? 2 dscp[91:90] ipv4 and ipv6 mapping _ for value 0xb4 r/w 00 1 ? 0 dscp[89:88] ipv4 and ipv6 mapping _ for value 0xb0 r/w 00 register 156 (0x9c): tos priority control register 12 address name description mode default 7 ? 6 dscp[103:102] ipv4 and ipv6 mapping _ for value 0xcc r/w 00 5 ? 4 dscp[101:100] ipv4 and ipv6 mapping _ for value 0xc8 r/w 00 3 ? 2 dscp[99:98] ipv4 and ipv6 mapping _ for value 0xc4 r/w 00 1 ? 0 dscp[97:96] ipv4 and ipv6 mapping _ for value 0xc0 r/w 00 register 157 (0x9d): tos priority control register 13 address name description mode default 7 ? 6 dscp[111:110] ipv4 and ipv6 mapping _ for value 0xdc r/w 00 5 ? 4 dscp[109:108] ipv4 and ipv6 mapping _ for value 0xd8 r/w 00 3 ? 2 dscp[107:106] ipv4 and ipv6 mapping _ for value 0xd4 r/w 00 1 ? 0 dscp[105:104] ipv4 and ipv6 mapping _ for value 0xd0 r/w 00
micrel, inc. KSZ8895MLU october 2011 75 m9999-100311-1.1 advanced control registers (continued) register 158 (0x9e): tos priority control register 14 address name description mode default 7 ? 6 dscp[119:118] ipv4 and ipv6 mapping _ for value 0xec r/w 00 5 ? 4 dscp[117:116] ipv4 and ipv6 mapping _ for value 0xe8 r/w 00 3 ? 2 dscp[115:114] ipv4 and ipv6 mapping _ for value 0xe4 r/w 00 1 ? 0 dscp[113:112] ipv4 and ipv6 mapping _ for value 0xe0 r/w 00 register 159 (0x9f): tos priority control register 15 address name description mode default 7 ? 6 dscp[127:126] ipv4 and ipv6 mapping _ for value 0xfc r/w 00 5 ? 4 dscp[125:124] ipv4 and ipv6 mapping _ for value 0xf8 r/w 00 3 ? 2 dscp[123:122] ipv4 and ipv6 mapping _ for value 0xf4 r/w 00 1 ? 0 dscp[121:120] ipv4 and ipv6 mapping _ for value 0xf0 r/w 00 register 176 (0xb0): port 1 control 8 register 192 (0xc0): port 2 control 8 register 208 (0xd0): port 3 control 8 register 224 (0xe0): port 4 control 8 register 240 (0xf0): port 5 control 8 address name description mode default 7 ? 4 reserved ro 0000 3 insert source port pvid for untagged packet destination to highest egress port note : enabled by the register 135 bit 2 register 176: insert sour ce port 1 pvid for untagged frame at egress port 5 register 192: insert sour ce port 2 pvid for untagged frame at egress port 5 register 208: insert sour ce port 3 pvid for untagged frame at egress port 5 register 224: insert sour ce port 4 pvid for untagged frame at egress port 5 register 240: insert sour ce port 5 pvid for untagged frame at egress port 4 r/w 0 2 insert source port pvid for untagged packet destination to second highest egress port note : enabled by the register 135 bit 2 register 176: insert sour ce port 1 pvid for untagged frame at egress port 4 register 192: insert sour ce port 2 pvid for untagged frame at egress port 4 register 208: insert sour ce port 3 pvid for untagged frame at egress port 4 register 224: insert sour ce port 4 pvid for untagged frame at egress port 3 register 240: insert sour ce port 5 pvid for untagged frame at egress port 3 r/w 0
micrel, inc. KSZ8895MLU october 2011 76 m9999-100311-1.1 advanced control registers (continued) register 176 (0xb0): port 1 control 8 register 192 (0xc0): port 2 control 8 register 208 (0xd0): port 3 control 8 register 224 (0xe0): port 4 control 8 register 240 (0xf0): port 5 control 8 address name description mode default 1 insert source port pvid for untagged packet destination to second lowest egress port note: enabled by the register 135 bit 2 register 176: insert sour ce port 1 pvid for untagged frame at egress port 3 register 192: insert sour ce port 2 pvid for untagged frame at egress port 3 register 208: insert sour ce port 3 pvid for untagged frame at egress port 2 register 224: insert sour ce port 4 pvid for untagged frame at egress port 2 register 240: insert sour ce port 5 pvid for untagged frame at egress port 2 r/w 0 0 insert source port pvid for untagged packet destination to lowest egress port note : enabled by the register 135 bit 2 register 176: insert sour ce port 1 pvid for untagged frame at egress port 2 register 192: insert sour ce port 2 pvid for untagged frame at egress port 1 register 208: insert sour ce port 3 pvid for untagged frame at egress port 1 register 224: insert sour ce port 4 pvid for untagged frame at egress port 1 register 240: insert sour ce port 5 pvid for untagged frame at egress port 1 r/w 0 register 177 (0xb1): port 1 control 9 register 193 (0xc1): port 2 control 9 register 209 (0xd1): port 3 control 9 register 225 (0xe1): port 4 control 9 register 241 (0xf1): port 5 control 9 address name description mode default 7 ? 2 reserved ro 0000000 1 4 queue split enable this bit in combination wi th register16/32/48/64/80 bit 0 will select the split of 1/2/4 queues: {register177 bit 1, register16 bit 0}= 11, reserved. 10, the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. 01, the port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. 00, single output queue on the port. there is no priority differentiation even though packets are classified into high and low priority r/w 0 0 enable dropping tag 0 = disable tag drop 1 = enable tag drop r/w 0
micrel, inc. KSZ8895MLU october 2011 77 m9999-100311-1.1 advanced control registers (continued) register 178 (0xb2): port 1 control 10 register 194 (0xc2): port 2 control 10 register 210 (0xd2): port 3 control 10 register 226 (0xe2): port 4 control 10 register 242 (0xf2): port 5 control 10 address name description mode default 7 enable port transmit queue 3 ratio 0, strict priority, will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1, bit[6:0] reflect the packe t number allow to transmit from this priority queue 3 within a certain time r/w 1 6 - 0 port transmit queue 3 ratio[6:0] packet number for transmit queue 3 for highest priority packets in four queues mode r/w 0001000 register 179 (0xb3): port 1 control 11 register 195 (0xc3): port 2 control 11 register 211 (0xd3): port 3 control 11 register 227 (0xe3): port 4 control 11 register 243 (0xf3): port 5 control 11 address name description mode default 7 enable port transmit queue 2 ratio 0, strict priority, will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1, bit[6:0] reflect the packe t number allow to transmit from this priority queue 1 within a certain time r/w 1 6 ? 0 port transmit queue 2 ratio[6:0] packet number for transmit queue 2 for high/low priority packets in high/low priority packets in four queues mode r/w 0000100 register 180 (0xb4): port 1 control 12 register 196 (0xc4): port 2 control 12 register 212 (0xd4): port 3 control 12 register 228 (0xe4): port 4 control 12 register 244 (0xf4): port 5 control 12 address name description mode default 7 enable port transmit queue 1 rate 0, strict priority, will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1, bit[6:0] reflect the packe t number allow to transmit from this priority queue 1 within a certain time r/w 1 6 ? 0 port transmit queue 1 ratio[6:0] packet number for transmit queue 1 for low/high priority packets in four queues mode and high priority packets in two queues mode r/w 0000010
micrel, inc. KSZ8895MLU october 2011 78 m9999-100311-1.1 advanced control registers (continued) register 181 (0xb5): port 1 control 13 register 197 (0xc5): port 2 control 13 register 213 (0xd5): port 3 control 13 register 229 (0xe5): port 4 control 13 register 245 (0xf5): port 5 control 13 address name description mode default 7 enable port transmit queue 0 rate 0, strict priority, will transmit all the packets from this priority queue 0 before transmit lower priority queue. 1, bit[6:0] reflect the packe t number allow to transmit from this priority queue 0 within a certain time r/w 1 6 ? 0 port transmit queue 0 ratio[6:0] packet number for transmit queue 0 for lowest priority packets in four queues mode and low priority packets in two queues mode r/w 0000001 register 182 (0xb6): port 1 rate limit control register 198 (0xc6): port 2 rate limit control register 214 (0xd6): port 3 rate limit control register 230 (0xe6): port 4 rate limit control register 246 (0xf6): port 5 rate limit control address name description mode default 7 ? 5 reserved ro 000 4 ingress rate limit flow control enable 1 = flow control is asserted if the port?s receive rate is exceeded 0 = flow control is not asserted if the port?s receive rate is exceeded r/w 0 3 ? 2 limit mode ingress limit mode these bits determine what ki nds of frames are limited and counted against ingress rate limiting. = 00, limit and count all frames = 01, limit and count broadcast, multicast, and flooded unicast frames = 10, limit and count broadcast and multicast frames only = 11, limit and count broadcast frames only r/w 00 1 count ifg count ifg bytes = 1, each frame?s minimum inter frame gap (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. = 0, ifg bytes are not counted. r/w 0 0 count pre count preamble bytes = 1, each frame?s preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. = 0, preamble bytes are not counted. r/w 0
micrel, inc. KSZ8895MLU october 2011 79 m9999-100311-1.1 advanced control registers (continued) register 183 (0xb7): port 1 priority 0 ingress limit control 1 register 199 (0xc7): port 2 priority 0 ingress limit control 1 register 215 (0xd7): port 3 priority 0 ingress limit control 1 register 231 (0xe7): port 4 priority 0 ingress limit control 1 register 247 (0xf7): port 5 priority 0 ingress limit control 1 address name description mode default 7 reserved ro 0 6 ? 0 port-based priority 0 ingress limit ingress data rate limit for priority 0 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000 register 184 (0xb8): port 1 priority 1 ingress limit control 2 register 200 (0xc8): port 2 priority 1 ingress limit control 2 register 216 (0xd8): port 3 priority 1 ingress limit control 2 register 232 (0xe8): port 4 priority 1 ingress limit control 2 register 248 (0xf8): port 5 priority 1 ingress limit control 2 address name description mode default 7 reserved ro 0 6 ? 0 port-based priority 1 ingress limit ingress data rate limit for priority 1 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000 register 185 (0xb9): port 1 priority 2 ingress limit control 3 register 201 (0xc9): port 2 priority 2 ingress limit control 3 register 217 (0xd9): port 3 priority 2 ingress limit control 3 register 233 (0xe9): port 4 priority 2 ingress limit control 3 register 249 (0xf9): port 5 priority 2 ingress limit control 3 address name description mode default 7 reserved ro 0 6 ? 0 port-based priority 2 ingress limit ingress data rate limit for priority 2 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000
micrel, inc. KSZ8895MLU october 2011 80 m9999-100311-1.1 advanced control registers (continued) register 186 (0xba): port 1 priority 3 ingress limit control 4 register 202 (0xca): port 2 priority 3 ingress limit control 4 register 218 (0xda): port 3 priority 3 ingress limit control 4 register 234 (0xea): port 4 priority 3 ingress limit control 4 register 250 (0xfa): port 5 priority 3 ingress limit control 4 address name description mode default 7 reserved ro 0 6 ? 0 port-based priority 3 ingress limit ingress data rate limit for priority 3 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000 register 187 (0xbb): port 1 queue 0 egress limit control 1 register 203 (0xcb): port 2 queue 0 egress limit control 1 register 219 (0xdb): port 3 queue 0 egress limit control 1 register 235 (0xeb): port 4 queue 0 egress limit control 1 register 251 (0xfb): port 5 queue 0 egress limit control 1 address name description mode default 7 reserved ro 0 6 ? 0 port queue 0 egress limit egress data rate limit for priority 0 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egre ss limit control registers. in four queues mode, it is lowest priority. in two queues mode, it is low priority. r/w 0000000 register 188 (0xbc): port 1 queue 1 egress limit control 2 register 204 (0xcc): port 2 queue 1 egress limit control 2 register 220 (0xdc): port 3 queue 1 egress limit control 2 register 236 (0xec): port 4 queue 1 egress limit control 2 register 252 (0xfc): port 5 queue 1 egress limit control 2 address name description mode default 7 reserved ro 0 6 ? 0 port queue 1 egress limit egress data rate limit for priority 1 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egre ss limit control registers. in four queues mode, it is low/high priority. in two queues mode, it is high priority. r/w 0000000
micrel, inc. KSZ8895MLU october 2011 81 m9999-100311-1.1 advanced control registers (continued) register 189 (0xbd): port 1 queue 2 egress limit control 3 register 205 (0xcd): port 2 queue 2 egress limit control 3 register 221 (0xdd): port 3 queue 2 egress limit control 3 register 237 (0xed): port 4 queue 2 egress limit control 3 register 253 (0xfd): port 5 queue 2 egress limit control 3 address name description mode default 7 reserved ro 0 6 ? 0 port queue 2 egress limit egress data rate limit for priority 2 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egre ss limit control registers. in four queues mode, it is high/low priority. r/w 0000000 register 190 (0xbe): port 1 queue 3 egress limit control 4 register 206 (0xce): port 2 queue 3 egress limit control 4 register 222 (0xde): port 3 queue 3 egress limit control 4 register 238 (0xee): port 4 queue 3 egress limit control 4 register 254 (0xfe): port 5 queue 3 egress limit control 4 address name description mode default 7 reserved ro 0 6 ? 0 port queue 3 egress limit egress data rate limit for priority 3 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egre ss limit control registers. in four queues mode, it is highest priority. r/w 0000000 note: 1. in the port priority 0-3 ingress rate limit mode, need to set all related ingress/egress ports to two queues or four queues mode. 2. in the port queue 0-3 egress rate limit mode, the highest priori ty get exact rate limit based on the rate select table, othe r priorities packets rate are based on the ratio of the port register control 10/11/12/13 when use more than one egress queue per port.
micrel, inc. KSZ8895MLU october 2011 82 m9999-100311-1.1 data rate selection table in 100bt rate for 100bt mode 1mbps <= rate <= 99mbps rate = 100 mbps less than 1mbps (see as below) priority/queue 0-3 ingress/egress limit control register bit[6:0] = decimal rate(decimal integer 1-99) 0 or 100 (decimal), ?0? is default value decimal 64 kbps 7?d101 128 kbps 7?d102 192 kbps 7?d103 256 kbps 7?d104 320 kbps 7?d105 384 kbps 7?d106 448 kbps 7?d107 512 kbps 7?d108 576 kbps 7?d109 640 kbps 7?d110 704 kbps 7?d111 768 kbps 7?d112 832 kbps 7?d113 896 kbps 7?d114 960 kbps 7?d115 data rate selection table in 10bt rate for 10bt mode 1mbps <= rate <= 9mbps rate = 10 mbps less than 1mbps (see as below) priority/queue 0-3 ingress/egress limit control register bit[6:0]= decimal rate(decimal integer 1-9) 0 or 10 (decimal), ?0? is default value decimal 64 kbps 7?d101 128 kbps 7?d102 192 kbps 7?d103 256 kbps 7?d104 320 kbps 7?d105 384 kbps 7?d106 448 kbps 7?d107 512 kbps 7?d108 576 kbps 7?d109 640 kbps 7?d110 704 kbps 7?d111 768 kbps 7?d112 832 kbps 7?d113 896 kbps 7?d114 960 kbps 7?d115
micrel, inc. KSZ8895MLU october 2011 83 m9999-100311-1.1 advanced control registers (continued) register 191(0xbf): testing register address name description mode default 7 ? 0 reserved n/a ro 00000000 register 207(0xcf): reserved control register address name description mode default 7 ? 0 reserved n/a don?t change ro 0x15 register 223(0xdf): test register 2 address name description mode default 7 ? 0 reserved r/w 00000000 register 239(0xef): test register 3 address name description mode default 7 reserved n/a don?t change ro 0 6 reserved n/a don?t change ro 0 5 reserved n/a don?t change ro 1 4 ? 0 reserved n/a don?t change ro 0x12 register 255(0xff): testing register4 address name description mode default 7 ? 0 reserved n/a don?t change ro 0x00
micrel, inc. KSZ8895MLU october 2011 84 m9999-100311-1.1 static mac address table KSZ8895MLU has a static and a dynamic address table. when a da look-up is requested, both tables will be searched to make a packet forwarding decision. when an sa look-up is re quested, only the dynamic table is searched for aging, migration, and learning purposes. the static da look-up result will have precedence over the dynamic da look-up result. if there are da matches in both tables, the result from the static table will be used. the static table can only be accessed and controlled by an external spi master (usually a processor). the entries in the static table will not be aged out by KSZ8895MLU. an external device does all addition, modificati on and deletion. register bit assignments are different for static mac table reads and static mac table write, as shown in table 11 and table 12. address name description mode default 63 ? 57 fid filter vlan id, representing one of the 128 active vlans ro 0000000 56 use fid 1, use (fid+mac) to look-up in static table. 0, use mac only to look-up in static table. ro 0 55 reserved reserved. ro n/a 54 override 1, override spanning tree ?transmit enable = 0? or ?receive enable = 0* setting. this bit is used for spanning tree implementation. 0, no override. ro 0 53 valid 1, this entry is valid, the look-up result will be used. 0, this entry is not valid. ro 0 52 ? 48 forwarding ports the 5 bits control the forward ports, example: 00001, forward to port 1 00010, forward to port 2 ?.. 10000, forward to port 5 00110, forward to port 2 and port 3 11111, broadcasting (excluding the ingress port) ro 00000 47 ? 0 mac address 48-bit mac address. ro 0x0 table 11. format of static mac table for read (32 entries) examples: (1) static address table read (read the 2nd entry) write to register 110 with 0x 10 (read static table selected) write to register 111 with 0x1 (trigger the read operation) then read register 113 (63 ? 56) read register 114 (55 ? 48) read register 115 (47 ? 40) read register 116 (39 ? 32) read register 117 (31 ? 24) read register 118 (23 ? 16) read register 119 (15 ? 8) read register 120 (7 ? 0)
micrel, inc. KSZ8895MLU october 2011 85 m9999-100311-1.1 address name description mode default 62 ? 56 fid filter vlan id, representing one of the 128 active vlans. w 0000000 55 use fid 1, use (fid+mac) to look-up in static table. 0, use mac only to look-up in static table. w 0 54 override 1, override spanning tree ?transmit enable = 0? or ?receive enable = 0? setting. this bit is used for spanning tree implementation. 0, no override. w 0 53 valid 1, this entry is valid, the look-up result will be used. 0, this entry is not valid. w 0 52 ? 48 forwarding ports the 5 bits control the forward ports, example: 00001, forward to port 1 00010, forward to port 2 ..... 10000, forward to port 5 00110, forward to port 2 and port 3 11111, broadcasting (excluding the ingress port) w 00000 47 ? 0 mac address 48-bit mac address. w 0x0 table 12. format of static mac table for writes (32 entries) examples: (2) static address table write (write the 8th entry) write to register 110 with 0x 10 (read static table selected) write register 113 (62 ? 56) write register 114 (55 ? 48) write register 115 (47 ? 40) write register 116 (39 ? 32) write register 117 (31 ? 24) write register 118 (23 ? 16) write register 119 (15 ? 8) write register 120 (7 ? 0) write to register 110 with 0x00 (write static table selected) write to register 111 with 0x7 (trigger the write operation)
micrel, inc. KSZ8895MLU october 2011 86 m9999-100311-1.1 vlan table the vlan table is used for vlan table look-up. if 802.1q vlan mode is enabled (register 5 bit 7 = 1), this table is used to retrieve vlan information that is associated with the ingres s packet. the fields includes fid (filter id), valid and vlan membership need initializtion, due to provide 4k spacing for t he vlan table, there is no vi d filed bits, vid is used as address index to input up to 4096 entries with bits [12:0] information. address name description mode initial value suggestion 12 valid 1, the entry is valid. 0, entry is invalid. r/w 0 11 ? 7 membership specify which ports are members of the vlan. if a da look-up fails (no match in both static and dynamic tables), the packet associated with this vlan will be forwarded to ports sp ecified in this field. e.g., 11001 means port 5, port 4 and port 1. r/w 11111 6 ? 0 fid filter id. KSZ8895MLU supports 128 active vlans represented by these seven bit fields. fid is the mapped id. if 802.1q vlan is enabled, the look-up in mac table will be based on fid+da and fid+sa. r/w 0 table 13. format of static vlan table (support max 4096 vlan id entries and 128 active vlans) if 802.1q vlan mode is enabled, KSZ8895MLU assigns a vid to every ingress packet when the packet is untagged or tagged with a null vid, the packet is assigned with the default port vid of the ingress port. if the packet is tagged with non-null vid, the vid in the tag is used. the look-up process starts from the vlan table look-up based on vid number. if the entry is not valid in vlan table, the packet is dropped and no address learning occurs. if t he entry is valid, the fid is retrieved. the fid+da and fid+sa lookups in mac tables are performed. the fid+da look-up determines the forwarding ports. if fid+da fails for look-up in mac table, the packet is broadcast to all the members or specified members (excluding the ingress port) based on the vlan tabl e. if fid+sa fails, the fid+ sa is learned. if want to communicate between different active vlans, set same fid, otherwise set different fid. the vlan table configuration is organized as 1024 vlan sets , each vlan set consists of 4 vlan entries, to support up to 4096 vlan entries. each vlan set has 52 bits and should be read or written at the same time specified by the indirect address. the vlan entries in the vlan set is mapped to indirect data registers as follow: entry0[12:0] maps to the vlan set bits[12 ? 0] {register119[4:0], register120[7:0]} entry1[12:0] maps to the vlan set bits[25 ? 13]{register117[1:0], register 118[7:0], register119[7:5]} entry2[12:0] maps to the vlan set bits[38 ? 26]{register116[6:0 ], register117[7:2]} entry3[12:0] maps to the vlan set bits[51 ? 39]{register114[3:0], regist er115[7:0], register116[7]}
micrel, inc. KSZ8895MLU october 2011 87 m9999-100311-1.1 in order to read one vlan entry, the vlan set is read first and the specific vlan entry info rmation can be extracted. to update any vlan entry, the vlan set is read first then only t he desired vlan entry is updated and the whole vlan set is written back. due to fid in vlan table is 7-bit, so the vlan table supports unique 128 flow vlan groups. each vlan set address is 10 bits long (maximum is 1024) in the i ndirect address register 110 and 111, the bit [9 ? 8] of vlan set address is at bit [1 ? 0] of register 110, and the bit [7 ? 0] of vlan set address is at bit [7-0] of register 111. each write and read can access to four consecutive vlan entries. examples : (1) vlan table read (read the vid=2 entry) write the indirect control and address registers first write to register 110 (0x6e) with 0x14 (read vlan table selected) write to register 111 (0x6f) with 0x0 (trigger the read operation for vid=0, 1, 2, 3 entries) then read the indirect data register s bits [38-26] for vid=2 entry read register 116 (0x74), (register116[6:0] are bits 12 ? 6 of vlan vid=2 entry) read register 117 (0x75), (register117[7:2] are bits 5 ? 0 of vlan vid=2 entry) (2) vlan table write (write the vid=10 entry) read the vlan set that contains vid=8, 9, 10, 11. write to register 110 (0x6e) with 0x14 (read vlan table selected) write to register 111 (0x6f) with 0x02 (trigger t he read operation and vid=8, 9, 10, 11 indirect address) read the vlan set first by the indirect dat a registers 114, 115, 116, 117, 118, 119, 120. modify the indirect data registers bits [38 ? 26] by the register 116 bit [6-0] and register 117 bit [7 ? 2] as follows: write to register 116 (0x74), (register116[6:0] are bits 12 ? 6 of vlan vid=10 entry) write to register 117 (0x75), (register117[7:2] are bits 5 ? 0 of vlan vid=10 entry) then write the indirect control and address registers write to register 110 (0x6e) with 0x04 (write vlan table selected) write to register 111 (0x6f) with 0x02 (trigger the write operation and vid=8, 9, 10, 11 indirect address) table 14 shows the relationship of the indirect address/data registers and vlan id.
micrel, inc. KSZ8895MLU october 2011 88 m9999-100311-1.1 indirect address high/low bit[9-0] for vlan sets indirect data registers bits for each vlan entry vid numbers vid bit[12-2] in vlan tag vid bit[1-0] in vlan tag 0 bits[12 ? 0] 0 0 0 0 bits[25 ? 13] 1 0 1 0 bits[38 ? 26] 2 0 2 0 bits[51 ? 39] 3 0 3 1 bits[12 ? 0] 4 1 0 1 bits[25 ? 13] 5 1 1 1 bits[38 ? 26] 6 1 2 1 bits[51 ? 39] 7 1 3 2 bits[12 ? 0] 8 2 0 2 bits[25 ? 13] 9 2 1 2 bits[38 ? 26] 10 2 2 2 bits[51 ? 39] 11 2 3 : : : : : : : : : : : : : : : 1023 bits[12 ? 0] 4092 1023 0 1023 bits[25 ? 13] 4093 1023 1 1023 bits[38 ? 26] 4094 1023 2 1023 bits[51 ? 39] 4095 1023 3 table 14. vlan id and indirect registers
micrel, inc. KSZ8895MLU october 2011 89 m9999-100311-1.1 dynamic mac address table table 15 is read only. the contents are maintained by the KSZ8895MLU only. address name description mode default 71 mac empty 1, there is no valid entry in the table. 0, there are valid entries in the table. ro 1 70 ? 61 no of valid entries indicates how many valid entries in the table. 0x3ff means 1k entries 0x1 and bit 71 = 0: means 2 entries 0x0 and bit 71 = 0: means 1 entry 0x0 and bit 71 = 1: means 0 entry ro 0 60 ? 59 time stamp 2-bit counters for internal aging ro 58 ? 56 source port the source port where fid+mac is learned. 000 port 1 001 port 2 010 port 3 011 port 4 100 port 5 ro 0x0 55 data ready 1, the entry is not ready, retr y until this bit is set to 0. 0, the entry is ready. ro 54 ? 48 fid filter id. ro 0x0 47 ? 0 mac address 48-bit mac address. ro 0x0 table 15. format of dynamic mac address table (1k entries)
micrel, inc. KSZ8895MLU october 2011 90 m9999-100311-1.1 dynamic mac address table read/write examples : (1) dynamic mac address table re ad (read the 1st entry), and retrieve the mac table size: write to register 110 with 0x18 (read dynamic table selected) write to register 111 with 0x0 (tri gger the read operation) and then read register 112 (71 ? 64) read register 113 (63 ? 56); // the above two registers show # of entries read register 114 (55 ? 48) // if bit 55 is 1, restart (reread) from this register read register 115 (47 ? 40) read register 116 (39 ? 32) read register 117 (31 ? 24) read register 118 (23 ? 16) read register 119 (15 ? 8) read register 120 (7 ? 0) (2) dynamic mac address table read (re ad the 257th entry), without retrie ving # of entries information: write to register 110 with 0x19 (read dynamic table selected) write to register 111 with 0x1 (tri gger the read operation) and then read register 112 (71 ? 64) read register 113 (63 ? 56) read register 114 (55 ? 48) // if bit 55 is 1, restart (reread) from this register read register 115 (47 ? 40) read register 116 (39 ? 32) read register 117 (31 ? 24) read register 118 (23 ? 16) read register 119 (15 ? 8) read register 120 (7 ? 0)
micrel, inc. KSZ8895MLU october 2011 91 m9999-100311-1.1 management information base (mib) counters the management information base (mib) counters are provided on per port basis. these co unters are read using indirect memory access as noted in the following tables: for port 1 offset counter name description 0x0 rxloprioritybyte rx lo-priority (d efault) octet count including bad packets. 0x1 rxhiprioritybyte rx hi-priority octet count including bad packets. 0x2 rxundersizepkt rx undersize packets w/good crc. 0x3 rxfragments rx fragment packets w/bad crc, symbol errors or alignment errors. 0x4 rxoversize rx oversize packets w/good crc (max: 1536 or 1522 bytes). 0x5 rxjabbers rx packets longer than 1522b w/either crc errors , alignment errors, or symbol errors (depends on max packet size setting) or rx packets longer than 1916b only. 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal preamble, packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/an integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x8 rxalignmenterror rx packets within (64,1522) bytes w/a non-integr al number of bytes and a bad crc (upper limit depends on max packet size setting). 0x9 rxcontrol8808pkts the number of mac control frames received by a port with 88-08h in ethertype field. 0xa rxpausepkts the number of pause frames received by a por t. pause frame is qualified with ethertype (88- 08h), da, control opcode (00 ? 01), data length (64b min), and a valid crc. 0xb rxbroadcast rx good broadcast pa ckets (not including errored broadcast packets or valid multicast packets). 0xc rxmulticast rx good multicast packets (not including mac cont rol frames, errored multicast packets or valid broadcast packets). 0xd rxunicast rx good unicast packets. 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length. 0xf rx65to127octets total rx packets (bad packets incl uded) that are between 65 and 127 octets in length. 0x10 rx128to255octets total rx packets (bad packets incl uded) that are between 128 and 255 octets in length. 0x11 rx256to511octets total rx packets (bad packets incl uded) that are between 256 and 511 octets in length. 0x12 rx512to1023octets total rx packets (bad packets incl uded) that are between 512 an d 1023 octets in length. 0x13 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting). 0x14 txloprioritybyte tx lo-priority good octet count, including pause packets. 0x15 txhiprioritybyte tx hi-priority good octet count, including pause packets. 0x16 txlatecollision the number of times a collision is det ected later than 512 bit-times into the tx of a packet. 0x17 txpausepkts the number of pause frames transmitted by a port. 0x18 txbroadcastpkts tx good broadcast packets (not incl uding errored broadcast or valid multicast packets). table 16. port 1 mib counter indirect memory offsets
micrel, inc. KSZ8895MLU october 2011 92 m9999-100311-1.1 for port 1 (continued) offset counter name description 0x19 txmulticastpkts tx good multicast packets (not includi ng errored multicast packets or valid broadcast packets). 0x1a txunicastpkts tx good unicast packets. 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium. 0x1c txtotalcollision tx total collision, half-duplex only. 0x1d txexcessivecollision a count of frames fo r which tx fails due to excessive collisions. 0x1e txsinglecollision successfully tx frames on a port for which tx is inhibited by exactly one collision. 0x1f txmultiplecollision successfully tx frames on a por t for which tx is inhibited by more than one collision. table 16. port 1 mib counter indirect memory offsets (continued) for port 2, the base is 0x20, same offset definition (0x20-0x3f) for port 3, the base is 0x40, same offset definition (0x40-0x5f) for port 4, the base is 0x60, same offset definition (0x60-0x7f) for port 5, the base is 0x80, same offset definition (0x80-0x9f) address name description mode default format of per port mib counters (16 entries) 31 overflow 1, counter overflow. 0, no counter overflow. ro 0 30 count valid 1, counter value is valid. 0, counter value is not valid. ro 0 29 ? 0 counter values counter value. ro 0 table 17. format of ?per port? mib counter offset counter name description 0x100 port1 tx drop packets tx packets dropped due to lack of resources. 0x101 port2 tx drop packets tx packets dropped due to lack of resources. 0x102 port3 tx drop packets tx packets dropped due to lack of resources. 0x103 port4 tx drop packets tx packets dropped due to lack of resources. 0x104 port5 tx drop packets tx packets dropped due to lack of resources. 0x105 port1 rx drop packets rx packe ts dropped due to lack of resources. 0x106 port2 rx drop packets rx packe ts dropped due to lack of resources. 0x107 port3 rx drop packets rx packe ts dropped due to lack of resources. 0x108 port4 rx drop packets rx packe ts dropped due to lack of resources. 0x109 port5 rx drop packets rx packe ts dropped due to lack of resources. table 18. all port dropped packet mib counters
micrel, inc. KSZ8895MLU october 2011 93 m9999-100311-1.1 address name description mode default 30 ? 16 reserved reserved. n/a n/a 15 ? 0 counter values counter value. ro 0 table 19. format of all dropped packet mib counters note that all port dropped packet mib counters do not indicate overflow or validity; ther efore the application must keep track of overflow and valid conditions. the KSZ8895MLU provides total 34 mib counter per port. these counter are used to monitor the port detail activity for network management and maintenance. these mib counters are read using indirect memory access as as noted in the following examples: programming examples: (1) mib counter read (read port 1 rx64octets counter) write to register 110 with 0x1c (read mib counters selected) write to register 111 with 0x e (trigger the read operation) then read register 117 (counter value 31 ? 24) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, restart (re read) from this register read register 118 (counter value 23 ? 16) read register 119 (counter value 15 ? 8) read register 120 (counter value 7 ? 0) (2) mib counter read (read port 2 rx64octets counter) write to register 110 with 0x1c (read mib counter selected) write to register 111 with 0x2e (trigger the read operation) then read register 117 (counter value 31 ? 24) //if bit 31 = 1, there was a counter overflow //if bit 30 = 0, restart (reread) from this register read register 118 (counter value 23 ? 16) read register 119 (counter value 15 ? 8) read register 120 (counter value 7 ? 0)
micrel, inc. KSZ8895MLU october 2011 94 m9999-100311-1.1 programming examples (continued): (3) mib counter read (read port 1 tx drop packets) write to register 110 with 0x1d write to register 111 with 0x00 then read register 119 (counter value 15 ? 8) read register 120 (counter value 7 ? 0) note that to read out all the counters, the best performance ov er the spi bus is (160+3) 8 80 = 104us, where there are 160 registers, 3 overhead, 8 clocks per acce ss, at 12.5mhz. in the heaviest conditi on, the byte counter will overflow in 2 minutes. it is recommended that the software read all the coun ters at least every 30 seconds. the per port mib counters are designed as ?read clear.? a per port mib counter will be cl eared after it is accessed. all port dropped packet mib counters are not cleared after they are accessed. the applicati on needs to keep track of overflow and valid conditions on these counters.
micrel, inc. KSZ8895MLU october 2011 95 m9999-100311-1.1 miim registers all the registers defined in this section can be also acce ssed via the spi interface. note that different mapping mechanisms are used for miim and spi. the ?phyad? defined in ieee is assigned as ?0x1? for port 1, ?0x2? for port 2, ?0x3? for port 3 and ?0x4? for port 4.. the ?regad? suppo rted are 0x0-0x5 (0h-5h), 0x1d (1dh) and 0x1f (1fh). register 0h: mii control address name description mode default 15 soft reset 1, phy soft reset. 0, normal operation. r/w (sc) 0 14 loop back 1 = perform mac loopback, loop back path as follows: assume the loop-back is at port 1 mac, port 2 is the monitor port. port 1 mac loopback (port 1 reg. 0, bit 14 = ?1?) start: rxp2/rxm2 (port 2). can also start from port 3, 4, 5 loopback: mac/phy interface of port 1?s mac end: txp2/txm2 (port 2). can also end at port 3, 4, 5 respectively setting address ox3,4,5 reg. 0, bit 14 = ?1? will perform mac loopback on port 3, 4, 5 respectively. 0 = normal operation. r/w 0 13 force 100 1, 100mbps. 0, 10mbps. r/w 1 12 an enable 1, auto-negotiation enabled. 0, auto-negotiation disabled. r/w 1 11 power down 1, power down. 0, normal operation. r/w 0 10 phy isolate 1, electrical phy isolation of phy from tx+/tx-. 0, normal operation. r/w 0 9 restart an 1, restart auto-negotiation. 0, normal operation. r/w 0 8 force full duplex 1, full duplex. 0, half duplex. r/w 0 7 collision test not supported. ro 0 6 reserved ro 0 5 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = micrel auto mdi/mdi-x mode r/w 1 4 force mdi 1, force mdi. 0, normal operation. r/w 0 3 disable auto mdi/mdi-x 1, disable auto mdi/mdi-x. 0, normal operation. r/w 0 2 disable far end fault 1, disable far end fault detection. 0, normal operation. r/w 0 1 disable transmit 1, disable transmit. 0, normal operation. r/w 0 0 disable led 1, disable led. 0, normal operation. r/w 0
micrel, inc. KSZ8895MLU october 2011 96 m9999-100311-1.1 miim registers (continued) register 1h: mii status address name description mode default 15 t4 capable 0, not 100 baset4 capable. ro 0 14 100 full capable 1, 100base-tx full-duplex capable. 0, not capable of 100base-tx full-duplex. ro 1 13 100 half capable 1, 100base-tx half-duplex capable. 0, not 100base-tx half-duplex capable. ro 1 12 10 full capable 1, 10base-t full-duplex capable. 0, not 10base-t full-duplex capable. ro 1 11 10 half capable 1, 10base-t half-duplex capable. 0, 10base-t half-duplex capable. ro 1 10 ? 7 reserved ro 0 6 preamble suppressed not supported. ro 0 5 an complete 1, auto-negotiation complete. 0, auto-negotiation not completed. ro 0 4 far end fault 1, far end fault detected. 0, no far end fault detected. ro 0 3 an capable 1, auto-negotiation capable. 0, not auto-negotiation capable. ro 1 2 link status 1, link is up. 0, link is down. ro 0 1 jabber test not supported. ro 0 0 extended capable 0, not extended register capable. ro 0 register 2h: phyid high address name description mode default 15 ? 0 phyid high high order phyid bits. ro 0x0022 register 3h: phyid low address name description mode default 15 ? 0 phyid low low order phyid bits. ro 0x1450
micrel, inc. KSZ8895MLU october 2011 97 m9999-100311-1.1 miim registers (continued) register 4h: advertisement ability address name description mode default 15 next page not supported. ro 0 14 reserved ro 0 13 remote fault not supported. ro 0 12 ? 11 reserved ro 0 10 pause 1, advertise pause ability. 0, do not advertise pause ability. r/w 1 9 reserved r/w 0 8 adv 100 full 1, advertise 100 full-duplex ability. 0, do not advertise 100 full-duplex ability. r/w 1 7 adv 100 half 1, advertise 100 half-duplex ability. 0, do not advertise 100 half-duplex ability. r/w 1 6 adv 10 full 1, advertise 10 full-duplex ability. 0, do not advertise 10 full-duplex ability. r/w 1 5 adv 10 half 1, advertise 10 half-duplex ability. 0, do not advertise 10 half-duplex ability. r/w 1 4 ? 0 selector field 802.3 ro 00001 register 5h: link partner ability address name description mode default 15 next page not supported. ro 0 14 lp ack not supported. ro 0 13 remote fault not supported. ro 0 12 ? 11 reserved ro 0 10 pause link partner pause capability. ro 0 9 reserved ro 0 8 adv 100 full link partner 100 full capability. ro 0 7 adv 100 half link partner 100 half capability. ro 0 6 adv 10 full link partner 10 full capability. ro 0 5 adv 10 half link partner 10 half capability. ro 0 4-0 reserved ro 00001
micrel, inc. KSZ8895MLU october 2011 98 m9999-100311-1.1 miim registers (continued) register 1dh: reserved address name description mode default 15 ? 0 reserved ro 0x0000 register 1fh: phy s pecial control/status address name description mode default 15 ? 11 reserved ro 0000000000 10-8 port operation mode indication indicate the current stat e of port operation mode: [000] = reserved [001] = still in auto-negotiation [010] = 10base-t half duplex [011] = 100base-tx half duplex [100] = reserved [101] = 10base-t full duplex [110] = 100base-tx full duplex [111] = phy/mii isolate ro 000 7-6 reserved n/a, don?t change r/w xx 5 polrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 mdi-x status 1 = mdi 0 = mdi-x ro 0 3 force_lnk 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power save 0 = disable power save r/w 0 1 remote loopback 1 = perform remote loopback, loop back path as follows: port 1 (phy id address 0x1 reg. 1f, bit 1 = ?1?) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1?s phy end: txp1/txm1 (port 1) setting phy id address 0x2,3,4,5 reg. 1fh, bit 1 = ?1? will perform remote loopback on port 2, 3, 4, 5. 0 = normal operation. r/w 0 0 reserved ro 0
micrel, inc. KSZ8895MLU october 2011 99 m9999-100311-1.1 absolute maximum ratings (1) supply voltage (v ddar , v ddap , v ddc ) .........................?0.5v to +2.4v (v ddat , v ddio ) ...................................?0.5v to +4.0v input volt age .......................................... ?0.5v to +4.0v output voltage .......................................?0.5v to +4.0v lead temperature (solder ing, 10 sec.)............... 260c storage temperature (t s ).................. ?55c to +150c hbm esd rating .................................................1.5kv operating ratings (2) supply voltage (v ddar , v ddap , v ddc )........................ +1.15v to +1.25v (v ddat ) ............................................ +3.15v to +3.45v (v ddio ) .. 3.15 to 3.45v or 2.4 to 2.6v or 1.71 to 1.89v ambient temperature (t a ) industrial ............................................ ?40c to +85c package thermal resistance (3) lqfp ( ja ) no air fl ow .............................41. 54c/w lqfp ( jc ) no air fl ow..............................19.78c/w electrical characteristics (4, 5) v in = 1.2v/3.3v (typ.); t a = 25c. symbol parameter condition min. typ. max. units 100base-tx operation?all ports 100% utilization i dx 100base-tx (transmitter) 3.3v analog v ddat 129 ma i dda 100base-tx 1.2v analog v ddar 40 ma i ddc 100base-tx 1.2v digital v ddc 45 ma i ddio 100base-tx (digital io) 3.3v digital v ddio 2.5 ma 10base-t operation ?all ports 100% utilization i dx 10base-t (transmitter) 3.3v analog v ddat 124 ma i dda 10base-t 1.2v analog v ddar 15 ma i ddc 10base-t 1.2v digital v ddc 56 ma i ddio 10base-t (digital io) 3.3v digital v ddio 2 ma auto-negotiation mode i dx 10base-t (transmitter) 3.3v analog v ddat 75 ma i dda 10base-t 1.2v analog v ddar 39 ma i edm 10base-t 1.2v digital v ddc 58 ma i ddio 10base-t (digital io) 3.3v digital v ddio 1.6 ma power management mode i psm1 power saving mode 3.3v v ddat + v ddio 38 ma i psm2 power saving mode 1.2v v ddar + vddc 73 ma i spdm1 soft power down mode 3.3v v ddat + v ddio 1.6 ma i spdm2 soft power down mode 1.2v v ddar + vddc 0.8 ma i edm1 energy detect mode 3.3v v ddat + v ddio 7.5 ma i edm2 energy detect mode 1.2v v ddar + vddc 46 ma notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to functi on outside its operating rating. unused inputs must always be tied to an appropriate l ogic voltage level (ground or v dd ). 3. no heat spreader in package. the thermal junction to ambient ( ja ) and the thermal junction to case ( jc ) are under air velocity 0m/s. 4. specification for packaged product only. there is no an additi onal transformer consumption due to use on chip termination te chnology with internal biasing for 10bese- t and 100base-tx. 5. measurements were taken with operating ratings.
micrel, inc. KSZ8895MLU october 2011 100 m9999-100311-1.1 electrical characteristics (4, 5) (continued) v in = 1.2v/3.3v (typ.); t a = 25c. symbol parameter condition min. typ. max. units ttl inputs v ih input high voltage 2.0/2.0/1.3 v v il input low voltage 0.8/0.6/0.3 v i in input current (excluding pull-up/pull-down) v in = gnd ~ v ddio ?10 10 a ttl outputs v oh output high voltage i oh = ?8ma 2.4/1.9/1.5 v v ol output low voltage i ol = 8ma 0.4/0.4/0.2 v i oz output tri-state leakage v in = gnd ~ v ddio 10 a 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 ? termination on the differential output 0.95 1.05 v v imb output voltage imbalance 100 ? termination on the differential output 2 % rise/fall time 3 5 ns t r t t rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.5 ns overshoot 5 % output jitters peak-to-peak 0 0.75 1.4 ns 10base-t receive v sq squelch threshold 5mhz square wave 300 400 585 mv 10base-t transmit (measured differentially after 1:1 transformer) v ddat = 3.3v v p peak differential output voltage 100 ? termination on the differential output 2.2 2.5 2.8 v output jitters peak-to-peak 1.4 3.5 ns rise/fall times 28 30 ns
micrel, inc. KSZ8895MLU october 2011 101 m9999-100311-1.1 timing diagrams eeprom timing figure 13. eeprom interface input receive timing diagram figure 14. eeprom interface output transmit timing diagram symbol parameter min. typ. max. units t cyc1 clock cycle 16384 ns t s1 set-up time 20 ns t h1 hold time 20 ns t ov1 output valid 4096 4112 4128 ns table 20. eeprom timing parameters
micrel, inc. KSZ8895MLU october 2011 102 m9999-100311-1.1 timing diagrams (continued) sni timing figure 15. sni input timing figure 16. sni output timing symbol parameter min. typ. max. units t cyc2 clock cycle 100 ns t s2 set-up time 10 ns t h2 hold time 0 ns t o2 output valid 0 3 6 ns table 21. sni timing parameters
micrel, inc. KSZ8895MLU october 2011 103 m9999-100311-1.1 timing diagrams (continued) mii timing figure 19. mac mode mii timing ? data received from mii figure 20. mac mode mii timing parameters 10base-t/100-base-tx symbol parameter min. typ. max. units t cyc3 clock cycle 400/40 ns t s3 set-up time 10 ns t h3 hold time 5 ns t o3 output valid 3 9 25 ns table 22. mac mode timing parameters
micrel, inc. KSZ8895MLU october 2011 104 m9999-100311-1.1 timing diagrams (continued) spi timing figure 21. spi input timing symbol parameter min. typ. max. units f c clock frequency 25 mhz t chsl spis_n inactive hold time 10 ns t slch spis_n active set-up time 10 ns t chsh spis_n active hold time 10 ns t shch spis_n inactive set-up time 10 ns t shsl spis_n deselect time 200 ns t dvch data input set-up time 5 ns t chdx data input hold time 5 ns t clch clock rise time 1 s t chcl clock fall time 1 s t dldh data input rise time 1 s t dhdl data input fall time 1 s table 23. spi input timing parameters
micrel, inc. KSZ8895MLU october 2011 105 m9999-100311-1.1 timing diagrams (continued) spi timing (continued) figure 22. spi output timing symbol parameter min. typ. max. units f c clock frequency 25 mhz t clqx spiq hold time 0 0 ns t clqv clock low to spiq valid 15 ns t ch clock high time 18 ns t cl clock low time 18 ns t qlqh spiq rise time 50 ns t qhql spiq fall time 50 ns t shqz spiq disable time 15 ns table 24. spi output timing parameters
micrel, inc. KSZ8895MLU october 2011 106 m9999-100311-1.1 timing diagrams (continued) auto-negotiation timing figure 23. auto-negotiation timing symbols parameters min. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per burst 17 33 table 24. auto-negotiation timing parameters
micrel, inc. KSZ8895MLU october 2011 107 m9999-100311-1.1 timing diagrams (continued) reset timing figure 24. reset timing symbol parameter min. typ. max. units t sr stable supply voltages to reset high 10 ms t cs configuration set-up time 50 ns t ch configuration hold time 50 ns t rc reset to strap-in pin output 50 ns tvr 3.3v rise time 100 s table 25. reset timing parameters
micrel, inc. KSZ8895MLU october 2011 108 m9999-100311-1.1 reset circuit diagram micrel recommends the following discrete reset circuit as shown in figure 25 when powering up the ks8895mq device. for the application where the reset circuit signal comes from another device (e.g., cpu, fpga, etc), we recommend the reset circuit as shown in figure 26. figure 25. recommended reset circuit figure 26. recommended circuit for interfacing with cpu/fpga reset at power-on-reset, r, c, and d1 provide the necessary ramp rise time to reset the micrel device. the reset out rst_out_n from cpu/fpga provides the warm reset after power up.
micrel, inc. KSZ8895MLU october 2011 109 m9999-100311-1.1 isolation transformer selection one simple 1:1 isolation transformer is needed at the line in terface. an isolation transformer with integrated common- mode choke is recommended for exceeding fcc requirements at line side. request to separate the center taps of rx/tx at chip side. table 26 gives recomm ended transformer characteristics. characteristics name value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350h 100mv, 100khz, 8ma leakage inductance (max.) 0.4h 1mhz (min.) inter-winding capacitance (max.) 12pf d.c. resistance (max.) 0.9 ? insertion loss (max.) 1.0db 0mhz to 65mhz hipot (min.) 1500vrms note: 1. the ieee 802.3u standard for 100base-tx assumes a transformer lo ss of 0.5db. for the transmit line transformer, insertion lo ss of up to 1.3db can be compensated by increasing the line drive current by means of reducing the iset resistor value. 2. the center taps of rx and tx should be isolated for the low power consumption. table 26. qualified magnetic vendors table 27 provide transformer vendors provide com patible magnetic parts for micrel?s device. vendors and parts auto mdix # of ports vendors and parts auto mdix # of ports pulse h1664nl yes 4 pulse h1102 yes 1 ycl ph406082 yes 4 bel fuse s558-5999-u7 yes 1 tdk tla-6t718a yes 1 ycl pt163020 yes 1 lankom lf-h41s yes 1 transpower hb726 yes 1 datatronic nt79075 yes 1 delta lf8505 yes 1 table 27. qualified magnetic vendors reference crystal selection chacteristics value units frequency 25.00000 mhz frequency tolerance (max.) ? = ? 50 ppm load capacitance (max.) 18 ? 27 pf series resistance 40 ? table 28. typical reference crystal characteristics
micrel, inc. KSZ8895MLU october 2011 110 m9999-100311-1.1 package information 128-pin lqfp micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether expre ss, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of an y patent, copyright or other intellectual p roperty right. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2011 micrel , incor p orated.

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